research-article

Public Access

Fast Power and Energy Management for Future Many-Core Systems

Authors:

Stark C. Draper,

Ricardo BianchiniAuthors Info & Claims

ACM Transactions on Modeling and Performance Evaluation of Computing Systems (TOMPECS), Volume 2, Issue 3

Article No.: 17, Pages 1 - 31

https://doi.org/10.1145/3086504

Published: 05 September 2017 Publication History

Abstract

Future servers will incorporate many active low-power modes for each core and for the main memory subsystem. Though these modes provide flexibility for power and/or energy management via Dynamic Voltage and Frequency Scaling (DVFS), prior work has shown that they must be managed in a coordinated manner. This requirement creates a combinatorial space of possible power mode configurations. As a result, it becomes increasingly challenging to quickly select the configuration that optimizes for both performance and power/energy efficiency.

In this article, we propose a novel queuing model for working with the abundant active low-power modes in many-core systems. Based on the queuing model, we derive two fast algorithms that optimize for performance and efficiency using both CPU and memory DVFS. Our first algorithm, called FastCap, maximizes the performance of applications under a full-system power cap, while promoting fairness across applications. Our second algorithm, called FastEnergy, maximizes the full-system energy savings under predefined application performance loss bounds. Both FastCap and FastEnergy operate online and efficiently, using a small set of performance counters as input. To evaluate them, we simulate both algorithms for a many-core server running different types of workloads. Our results show that FastCap achieves better application performance and fairness than prior power capping techniques for the same power budget, whereas FastEnergy conserves more energy than prior energy management techniques for the same performance constraint. FastCap and FastEnergy together demonstrate the applicability of the queuing model for managing the abundant active low-power modes in many-core systems.

References

[1]

D. Abts, M. R. Marty, P. M. Wells, P. Klausler, and H. Liu. 2010. Energy proportional datacenter networks. In ACM Proceedings of International Symposium on Computer Architecture.

Digital Library

[2]

I. F. Akyildiz. 1988. On the exact and approximate throughput analysis of closed queuing networks with blocking. IEEE Transactions on Software Engineering 14, 1, 62--70.

Digital Library

[3]

S. Balsamo, V. D. N. Persone, and R. Onvural. 2001. Analysis of Queuing Networks with Blocking. Springer.

Digital Library

[4]

N. Bansal, T. Kimbrel, and K. Pruhs. 2007. Speed scaling to manage energy and temperature. Journal of the ACM 54, 1, Article No. 3.

Digital Library

[5]

R. Begum, M. Hempstead, G. P. Srinivasa, and G. Challen. 2016. Algorithms for CPU and DRAM DVFS under inefficiency constraints. In Proceedings of the IEEE International Conference on Computer Design.

[6]

R. Bergamaschi, G. Han, A. Buyuktosunoglu, H. Patel, and I. Nair. 2008. Exploring power management in multi-core systems. In Proceedings of the ACM/EDAC/IEEE Design Automation Conference.

Digital Library

[7]

P. Bose, A. Buyuktosunoglu, J. A. Darringer, M. S. Gupta, M. B. Healy, H. Jacobson, I. Nair, J. A. Rivers, J. Shin, A. Vega, and A. J. Weger. 2012. Power management of multi-core chips: Challenges and pitfalls. In Proceedings of the IEEE Design, Automation and Test in Europe.

Digital Library

[8]

E. V. Carrera, E. Pinheiro, and R. Bianchini. 2003. Conserving disk energy in network servers. In ACM Proceedings of International Conference on Supercomputing.

Digital Library

[9]

J. M. Cebrian, J. L. Aragon, and S. Kaxiras. 2011. Power token balancing: Adapting CMPs to power constraints for parallel multithreaded workloads. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium.

Digital Library

[10]

M. Chen, X. Wang, and X. Li. 2011. Coordinating processor and main memory for efficient server power control. In Proceedings of the ACM International Conference on Supercomputing.

Digital Library

[11]

H. David, C. Fallin, E. Gorbatov, U. Hanebutte, and O. Mutlu. 2011. Memory power management via dynamic voltage/frequency scaling. In Proceedings of the ACM International Conference on Autonomic Computing.

Digital Library

[12]

M. Dayarathna, Y. Wen, and R. Fan. 2015. Data center energy consumption modeling: A survey. In IEEE Communications Surveys 8 Tutorials.

[13]

Q. Deng, D. Meisner, A. Bhattacharjee, T. F. Wenisch, and R. Bianchini. 2012. CoScale: Coordinating CPU and Memory DVFS in server systems. In Proceedings of IEEE/ACM International Symposium on Microarchitecture.

Digital Library

[14]

Q. Deng, D. Meisner, L. Ramos, T. F. Wenisch, and R. Bianchini. 2011. MemScale: Active low-power modes for main memory. In Proceedings of the ACM International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[15]

X. Fan, C. S. Ellis, and A. R. Lebeck. 2003. The synergy between power-aware memory systems and processor voltage scaling. In Proceedings of the ACM International Conference on Power-Aware Computer Systems.

Digital Library

[16]

A. Gandhi and M. Harchol-Balter. 2011. How data center size impacts the effectiveness of dynamic power management. In Proceedings of the IEEE Allerton Conference on Communication, Control, and Computing.

[17]

A. Gandhi, M. Harchol-Balter, R. Raghunathan, and M. A. Kozuch. 2012. AutoScale: Dynamic, robust capacity management for multi-tier data centers. ACM Transactions on Computer Systems 30, 4, Article No. 14.

Digital Library

[18]

S. Gurumurthi, A. Sivasubramaniam, M. Kandemir, and H. Franke. 2003. DRPM: Dynamic speed control for power management in server class disks. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

[19]

M. Harchol-Balter. 2013. Performance Modeling and Design of Computer Systems: Queueing Theory in Action. Cambridge University Press.

Digital Library

[20]

S. Herbert and D. Marculescu. 2007. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design.

Digital Library

[21]

C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. 2006. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of IEEE/ACM International Symposium on Microarchitecture.

Digital Library

[22]

JEDEC. 2009. DDR3 SDRAM Standard. (2009).

[23]

W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the IEEE Symposium on High Performance Computer Architecture.

[24]

X. Li, R. Gupta, S. Adve, and Y. Zhou. 2007. Cross-component energy management: Joint adaptation of processor and memory. ACM Transactions on Architecture and Code Optimization 4, 3, Article No. 14.

Digital Library

[25]

X. Li, Z. Li, F. M. David, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar. 2004. Performance-directed energy management for main memory and disks. In Proceedings of the ACM International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[26]

Y. Liu, G. Cox, Q. Deng, S. C. Draper, and R. Bianchini. 2016. FastCap: An efficient and fair algorithm for power capping in many-core systems. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems 8 Software.

[27]

Y. Liu, S. C. Draper, and N. S. Kim. 2013. Queuing theoretic analysis of power-performance tradeoff in power-efficient computing. In Proceedings of the IEEE Conference on Information Sciences and Systems.

[28]

Y. Liu, S. C. Draper, and N. S. Kim. 2014. SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

[29]

K. Ma, X. Li, M. Chen, and X. Wang. 2011. Scalable power control for many-core architectures running multi-threaded applications. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

[30]

D. Meisner, C. M. Sadler, L. A. Barroso, W.-D. Weber, and T. F. Wenisch. 2011. Power management of online data-intensive services. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

[31]

K. Meng, R. Joseph, R. P. Dick, and L. Shang. 2008. Multi-optimization power management for chip multiprocessors. In Proceedings of the ACM International Conference on Parallel Architectures and Compilation.

Digital Library

[32]

Micron. 2007. DDR3 SDRAM System-Power Calculator. Retrieved from http://tinyurl.com/hcddfw5.

[33]

A. K. Mishra, S. Srikantaiah, M. Kandemir, and C. R. Das. 2010. CPM in CMPs: Coordinated power management in chip multiprocessors. In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

Digital Library

[34]

H. Sasaki, A. Buyuktosunoglu, A. Vega, and P. Bose. 2016. Mitigating power contention: A scheduling based approach. In IEEE Computer Architecture Letters.

[35]

J. Sharkey, A. Buyuktosunoglu, and P. Bose. 2007. Evaluating design tradeoffs in on-chip power management for CMPs. In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design.

Digital Library

[36]

V. Spiliopoulos, S. Kaxiras, and G. Keramidas. 2011. Green governors: A framework for continuously adaptive DVFS. In Proceedings of the IEEE International Green Computing Conference.

Digital Library

[37]

R. Teodorescu and J. Torrellas. 2008. Variation-aware application scheduling and power management for chip multiprocessors. In ACM Proceedings of International Symposium on Computer Architecture.

Digital Library

[38]

A. Wierman, L. L. H. Andrew, and A. Tang. 2012. Power-aware speed scaling in processor sharing systems. In Performance Evaluation, Vol. 69. 601--622.

Digital Library

[39]

H. Wong. 2012. A Comparison of Intel’s 32nm and 22nm Core i5 CPUs: Power, Voltage, Temperature, and Frequency. Retrieved from http://tinyurl.com/z7rxjy3.

[40]

Q. Wu, Q. Deng, L. Ganesh, C.-H. Hsu, Y. Jin, S. Kumar, B. Li, J. Meza, and Y. J. Song. 2016. Dynamo: Facebook’s data center-wide power management system. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

[41]

G. Yan, Y. Li, Y. Han, X. Li, M. Guo, and X. Liang. 2012. AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. In Proceedings of the IEEE Symposium on High Performance Computer Architecture.

Digital Library

[42]

H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. 2009. Decoupled DIMM: Building high-bandwidth memory system using low-speed DRAM devices. In Proceedings of the ACM International Symposium on Computer Architecture.

Digital Library

Cited By

Wu SChen YWang XJin HLiu FChen HYan C(2021)Precise Power Capping for Latency-Sensitive Applications in DatacenterIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28818936:3(469-480)Online publication date: 1-Jul-2021
https://doi.org/10.1109/TSUSC.2018.2881893
Hou SNi WZhao SCheng BChen SChen J(2020)Decentralized Real-Time Optimization of Voltage Reconfigurable Cloud Computing Data CenterIEEE Transactions on Green Communications and Networking10.1109/TGCN.2020.29870634:2(577-592)Online publication date: Jun-2020
https://doi.org/10.1109/TGCN.2020.2987063
Saifullah ASankar SLiu JLu CChandra RPriyantha B(2018)CapNetACM Transactions on Sensor Networks10.1145/327862415:1(1-34)Online publication date: 15-Dec-2018
https://dl.acm.org/doi/10.1145/3278624
Show More Cited By

Index Terms

Fast Power and Energy Management for Future Many-Core Systems

Recommendations

Power Management of Datacenter Workloads Using Per-Core Power Gating

While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter ...
Distributed peak power management for many-core architectures
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Recently proposed techniques for peak power management [4] involve centralized decision-making and assume quick evaluation of the various power management states. These techniques do not prevent instantaneous power from exceeding the peak power budget, ...
Latency-aware DVFS for efficient power state transitions on many-core architectures

Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Modeling and Performance Evaluation of Computing Systems

ACM Transactions on Modeling and Performance Evaluation of Computing Systems Volume 2, Issue 3

September 2017

135 pages

ISSN:2376-3639

EISSN:2376-3647

DOI:10.1145/3119902

Editors:
Sem Borst
Nokia Bell Labs / Eindhoven University of Technology, Netherlands
,
Carey Williamson
University of Calgary, Canada

Issue’s Table of Contents

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 September 2017

Accepted: 01 April 2017

Revised: 01 January 2017

Received: 01 September 2016

Published in TOMPECS Volume 2, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tag

Queuing theory and optimization

Qualifiers

Research-article
Research
Refereed

Funding Sources

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
256
Total Downloads

Downloads (Last 12 months)27
Downloads (Last 6 weeks)4

Reflects downloads up to 16 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wu SChen YWang XJin HLiu FChen HYan C(2021)Precise Power Capping for Latency-Sensitive Applications in DatacenterIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28818936:3(469-480)Online publication date: 1-Jul-2021
https://doi.org/10.1109/TSUSC.2018.2881893
Hou SNi WZhao SCheng BChen SChen J(2020)Decentralized Real-Time Optimization of Voltage Reconfigurable Cloud Computing Data CenterIEEE Transactions on Green Communications and Networking10.1109/TGCN.2020.29870634:2(577-592)Online publication date: Jun-2020
https://doi.org/10.1109/TGCN.2020.2987063
Saifullah ASankar SLiu JLu CChandra RPriyantha B(2018)CapNetACM Transactions on Sensor Networks10.1145/327862415:1(1-34)Online publication date: 15-Dec-2018
https://dl.acm.org/doi/10.1145/3278624
Krzywda JAli-Eldin AWadbro EOstberg PElmroth E(2018)ALPACA: Application Performance Aware Server Power Capping2018 IEEE International Conference on Autonomic Computing (ICAC)10.1109/ICAC.2018.00014(41-50)Online publication date: Sep-2018
https://doi.org/10.1109/ICAC.2018.00014

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents