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IC analyses including extracted inductance models

Authors:

Michael W. Beattie,

Lawrence T. PileggiAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 915 - 920

https://doi.org/10.1145/309847.310098

Published: 01 June 1999 Publication History

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References

[1]

K. Kerns, I. Wemple, A. Yang, Stable and Efficient Reduction of Substrate Model Network using Congruence Transformation, Proc. ICCAD 1995 (Nov. 1995).

Digital Library

Google Scholar

[2]

A. Odabasioglu, M. Celik, L. Pileggi, PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm, Proc. ICCAD 1997 (Nov. 1997).

Digital Library

Google Scholar

[3]

L. Pillage, R. Rohrer, Asymptotic Waveform Evaluation for Timing Analysis, IEEE. Trans. Computer-Aided Design, 9, No. 4 (Apr. 1990).

Crossref

Google Scholar

[4]

L. Silveria, M. Kamon, J. White, Efficient Reduced- Order Modeling of Frequency-Dependent Coupling Inductance Associated with 3-D Interconnect Structure, Proc. 32 nd DAC (June 1995).

Digital Library

Google Scholar

[5]

A. Deutsch, et al., Modeling and characterization of long on-chip interconnections for high-performance microprocessors, IBM J. Res. Dev., 39, No. 5, pg. 547- 567 (Sept. 1995).

Digital Library

Google Scholar

[6]

F. Grover, Inductance Calculations, Dover Publications, New York (1946).

Google Scholar

[7]

M. Kamon, M. Tsuk, J. White, FASTHENRY: A Multipole Accelerated 3-D Inductance Extraction Program, IEEE Trans. Microwave Theory and Techniques, 42, No. 9, pp. 1750-1758 (Sept. 1994).

Crossref

Google Scholar

[8]

B. Krauter, L. Pileggi, Generating Sparse Partial Inductance Matrices with Guaranteed Stability, Proc. ICCAD 1996 (Nov. 1996).

Digital Library

Google Scholar

[9]

M. Beattie, L. Alatan, L. Pileggi, Equipotential Shells for Efficient Partial Inductance Extraction, Proc. 1998 IEDM (Dec. 1998).

Digital Library

Google Scholar

[10]

E. Rosa, The Self and Mutual Inductance of Linear Conductors, Bulletin of the National Bureau of Standards, 4, pp. 301-344 (1908).

Crossref

Google Scholar

[11]

A. Ruehli, Inductance Calculations in a Complex Integrated Circuit Environment, IBM J. Res. Dev., 16, No. 5, pg. 470-481 (Sept. 1972).

Digital Library

Google Scholar

[12]

W. Weeks, L. Wu, M. McAllister, A. Singh, Resistive and Inductive Skin Effect in Rectangular Conductors, IBM J. Res. Dev., 23, No. 6, pg. 652-660 (Nov. 1979).

Digital Library

Google Scholar

[13]

R. Arunachalam, F. Dartu and L. Pileggi, CMOS Gate Delay Models for General RLC Loading, Proc. ICCD 1997 (Oct. 1997).

Digital Library

Google Scholar

[14]

M. Kamon, N. Marques, L. Silveira, J. White, Generating Reduced Order Models via PEEC for Capturing Skin and Proximity Effects, Proc. 6 th Meeting on Electr. Perform. of Electr. Packaging, San Jose (Nov. 1997).

Google Scholar

[15]

D. Bailey, B. Benschneider, Clocking Design and Analysis for a 600-MHz Alpha Microprocessor, IEEE J. Solid-State Circuits, 33, No. 11 (Nov. 1998).

Crossref

Google Scholar

Cited By

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Beattie MPileggi L(2008)Efficient Inductance Extraction via WindowingDesign, Automation, and Test in Europe10.1007/978-1-4020-6488-3_27(377-388)Online publication date: 2008
https://doi.org/10.1007/978-1-4020-6488-3_27
Chen JHe LYasuura H(2003)Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnectsProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119804(162-167)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119804
Chen JHe LLaPotin DAlpert CLillis J(2002)Determination of worst-case crosstalk noise for non-switching victims in GHz+ busesProceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems10.1145/589411.589430(92-97)Online publication date: 2-Dec-2002
https://dl.acm.org/doi/10.1145/589411.589430
Show More Cited By

Index Terms

IC analyses including extracted inductance models
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Hardware validation
  2. Robustness

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1999

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DAC99

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SIGDA
IEEE-CAS

DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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June 22 - 26, 2025

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Cited By

View all

Beattie MPileggi L(2008)Efficient Inductance Extraction via WindowingDesign, Automation, and Test in Europe10.1007/978-1-4020-6488-3_27(377-388)Online publication date: 2008
https://doi.org/10.1007/978-1-4020-6488-3_27
Chen JHe LYasuura H(2003)Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnectsProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119804(162-167)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119804
Chen JHe LLaPotin DAlpert CLillis J(2002)Determination of worst-case crosstalk noise for non-switching victims in GHz+ busesProceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems10.1145/589411.589430(92-97)Online publication date: 2-Dec-2002
https://dl.acm.org/doi/10.1145/589411.589430
(2002)Physical Verification and Design Sign-offSystem-on-a-Chip Verification10.1007/0-306-46995-2_8(347-358)Online publication date: 2002
https://doi.org/10.1007/0-306-46995-2_8
Ma JHe LErnst R(2001)Formulae and applications of interconnect estimation considering shield insertion and net orderingProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603162(327-332)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603162
(2001)Impact of On-Chip Inductance When Transitioning from Al to Cu Based TechnologyProceedings of the 2nd International Symposium on Quality Electronic Design10.5555/558593.850121Online publication date: 26-Mar-2001
https://dl.acm.org/doi/10.5555/558593.850121
Chen T(2001)On the impact of on-chip inductance on signal nets under the influence of power grid noiseProceedings of the conference on Design, automation and test in Europe10.5555/367072.367308(451-459)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367308
Beattle MPileggi L(2001)Efficient inductance extraction via windowingProceedings of the conference on Design, automation and test in Europe10.5555/367072.367304(430-436)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367304
Banerjee KMehrotra ARabaey J(2001)Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnectsProceedings of the 38th annual Design Automation Conference10.1145/378239.379069(798-803)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379069
Beattie MPileggi LRabaey J(2001)Modeling magnetic coupling for on-chip interconnectProceedings of the 38th annual Design Automation Conference10.1145/378239.378504(335-340)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378504
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Figures of merit to characterize the importance of on-chip inductance

Inductance Modeling for On-Chip Interconnects

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