HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis

This paper presents an implementation of an Orthogonal Frequency-Division Multiplexing (OFDM) receiver using the high-level synthesis tool, from Xilinx called Software Defined System-on-Chip (SDSoC). The Zynq SoCs containing an ARM processor besides a Field Programmable Gate Array (FPGA) are introduced to improve the system performance and power efficiency. SDSoC provides an embedded C/C++ application programming interface for developing heterogeneous embedded systems. Thus, the OFDM receiver is written in C/C++ code to be realizable on the FPGA and the ARM processor. The OFDM receiver is composed of computationally intensive tasks which requires a HW/SW co-design to fulfill system requirements. In this work, the implementation of OFDM receiver blocks are evaluated on ZC706 board and compared against the Heterogeneous Accelerator-Rich Platform (HARP). Based on the achieved results, the complete execution of the IEEE 802.11a/g receiver shows an overall speed-up 3.49X compared to the HARP platform.