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Mixed-swing quadrail for low power dual-rail domino logic

Authors:

Bharath Ramasubramanian,

Herman Schmit,

L. Richard CarleyAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 82 - 84

https://doi.org/10.1145/313817.313864

Published: 17 August 1999 Publication History

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Cited By

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Heragu KSharma MKundu RBlanton R(2006)Test vector generation for charge sharing failures in dynamic logicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80437721:12(1502-1508)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.804377
Kundu RBlanton R(2003)ATPG for Noise-Induced Switch Failures in Domino LogicProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009974Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009974
Mader RKourtev IStan MGarrett DNakajima K(2003)Reduced dynamic swing domino logicProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764817(33-36)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764817
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Index Terms

Mixed-swing quadrail for low power dual-rail domino logic
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware

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Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 17 August 1999

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ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Heragu KSharma MKundu RBlanton R(2006)Test vector generation for charge sharing failures in dynamic logicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80437721:12(1502-1508)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.804377
Kundu RBlanton R(2003)ATPG for Noise-Induced Switch Failures in Domino LogicProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009974Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009974
Mader RKourtev IStan MGarrett DNakajima K(2003)Reduced dynamic swing domino logicProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764817(33-36)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764817
Kundu RBlanton R(2003)Path delay test generation for domino logic circuits in the presence of crosstalkInternational Test Conference, 2003. Proceedings. ITC 2003.10.1109/TEST.2003.1270832(122-130)Online publication date: 2003
https://doi.org/10.1109/TEST.2003.1270832
Kundu RBlanton R(2003)ATPG for noise-induced switch failures in domino logicICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159763(765-768)Online publication date: 2003
https://doi.org/10.1109/ICCAD.2003.159763
Jung SKim KKang SAckland B(2002)Low-swing clock domino logic incorporating dual supply and dual threshold voltagesProceedings of the 39th annual Design Automation Conference10.1145/513918.514036(467-472)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514036
Kundu RBlanton R(2002)Timed test generation for crosstalk switch failures in domino CMOSProceedings 20th IEEE VLSI Test Symposium (VTS 2002)10.1109/VTS.2002.1011168(379-385)Online publication date: 2002
https://doi.org/10.1109/VTS.2002.1011168
Seong-Ook Jung Ki-Wook Kim Sung-Mo Kang (2002)Low-swing clock domino logic incorporating dual supply and dual threshold voltagesProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)10.1109/DAC.2002.1012670(467-472)Online publication date: 2002
https://doi.org/10.1109/DAC.2002.1012670
Heragu KSharma MKundu RBlanton R(2001)Testing of dynamic logic circuits based on charge sharingProceedings 19th IEEE VLSI Test Symposium. VTS 200110.1109/VTS.2001.923468(396-403)Online publication date: 2001
https://doi.org/10.1109/VTS.2001.923468
Balczewski RHarjani R(2001)Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltagesISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)10.1109/ISCAS.2001.921904(508-511)Online publication date: 2001
https://doi.org/10.1109/ISCAS.2001.921904
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Design of Ternary Adiabatic Dual-Rail Domino Comparator

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