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The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study

Authors:

Thomas L. Martin,

Daniel P. SiewiorekAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 200 - 205

https://doi.org/10.1145/313817.313925

Published: 17 August 1999 Publication History

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References

[1]

A. Agarwal, Analysis of cache performance for operating systems and multiprogramming. Boston: Kluwer Academic Publishers, 1989.]]

Digital Library

Google Scholar

[2]

J. Anderson, L. Berc, J. Dean, S. Ghemawat, M. Henzinger, S. Leung, R. Sites, M. Vandevoorde, C. Waldspurger, W. Weihl, "Continuous profiling: Where have all the cycles gone?" ACM Transactions on Computer Systems, vol. 15, no.4, November 1997, p. 357-90.]]

Digital Library

Google Scholar

[3]

Benchmarq Microelectronics, Inc. 1998 Data Book. 1998.]]

Google Scholar

[4]

Digital Equipment Corporation. DIGITAL Semiconductor SA-1100 Microprocessor: Technical Reference Manual, revision EC-R5MTC-TE, March 1998.]]

Google Scholar

[5]

M. Doyle and J. Newman, "The Use of Mathematical Modeling in the Design of Lithium/Polymer Battery Systems," Electrochimica Acta, vol. 40, no. 13-14; 1995; pp. 2191-2196.]]

Crossref

Google Scholar

[6]

M. Doyle, J. Newman, and J. Reimers, "A quick method for measuring the capacity versus the discharge rate for a dual lithium-ion insertion cell undergoing cycling," Journal of Power Sources; vol. 52, no. 2; December 1994; pp. 211-216.]]

Crossref

Google Scholar

[7]

S. Graham, P. Kessler, M. McKusick, "gprof: A Call Graph Execution Profiler," Proceedings of the SIG- PLAN '82 Symposium on Compiler Construction, SIG- PLAN Notices, June 1982, Vol. 17, No. 6, pp. 120-126.]]

Digital Library

Google Scholar

[8]

K. Govil, E. Chan, and H. Wasserman, "Comparing Algorithms for Dynamic Speed-Setting of a Low- Power CPU," Proceedings of the 1st ACM International Conference on Mobile Computing and Networking, 1995, pp. 13-25.]]

Digital Library

Google Scholar

[9]

T. Kuroda, K. Suzuki, S. Mira, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, "Variable supply-voltage scheme for low-power high-speed CMOS digital design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998, pp. 454-462.]]

Crossref

Google Scholar

[10]

D. Linden, Handbook of Batteries, 2nd ed. New York: McGraw-Hill, Inc. 1995.]]

Google Scholar

[11]

T. Martin and D. Siewiorek, "A Power Metric for Mobile Systems," Proceedings of the 1996 International Symposium on Low Power Electronics and Design, August 1996, pp. 37-42.]]

Digital Library

Google Scholar

[12]

PC Magazine, "Travelling powerhouses," January 19, 1999.]]

Google Scholar

[13]

T. Pering and R. Brodersen, "Energy efficient voltage scheduling for real-time operating systems," Fourth iEEE Real-Time Technology and Applications Symposium, Works-In-Progress Session, June, 1998.]]

Google Scholar

[14]

Sanyo Corporation. UF812248 Data Sheet. April, 1998.]]

Google Scholar

[15]

Sanyo Corporation. UF612248 Data Sheet. April, 1998.]]

Google Scholar

[16]

R. Uhlig, D. Nagle, T. Mudge, S. Sechrest, and J. Emer, "Instruction Fetching: Coping with Code Bloat," Proceedings of the 22nd International Symposium on Computer Architecture, July 1995, pp. 345-356.]]

Digital Library

Google Scholar

[17]

M. Viredaz, "The Itsy Pocket Computer Version 1.5 User's Manual," Compaq Western Research Laboratory Technical Note TN-54, July 1998.]]

Google Scholar

[18]

M. Weiser, B. Welch, A. Demers, and S. Shenker, "Scheduling for Reduced CPU Energy," Proceedings of the 1st USENIX Symposium on Operating Systems Design and implementation, November 1994, pp. 13- 23.]]

Digital Library

Google Scholar

[19]

N. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2rid ed. Reading, MA: Addison-Wesley Publishing Company, 1993.]]

Digital Library

Google Scholar

[20]

F. Yao, A. Demers, and S. Shenker, "A Scheduling Model for Reduced CPU Energy," Proceedings of the 36th Annual Symposium on Foundations of Computer Science, October 1995, pp. 374-382.]]

Digital Library

Google Scholar

Cited By

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Siewiorek D(2017)Wearable ComputingGetMobile: Mobile Computing and Communications10.1145/3103535.310353721:1(5-10)Online publication date: 31-May-2017
https://dl.acm.org/doi/10.1145/3103535.3103537
Kuo CChien LLu YSuen CAghdam AGuo MHong JNadimi E(2013)Scheduling algorithm with energy-response trade-off considerations for mixed task setsProceedings of the 2013 Research in Adaptive and Convergent Systems10.1145/2513228.2513236(410-415)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2513228.2513236
Kremer U(2009)Low-Power/Energy Compiler OptimizationsLow-Power Processors and Systems on Chips10.1201/9781420037203.ch18(18-1-18-8)Online publication date: 4-Dec-2009
https://doi.org/10.1201/9781420037203.ch18
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The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study

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Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

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Publication History

Published: 17 August 1999

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ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Siewiorek D(2017)Wearable ComputingGetMobile: Mobile Computing and Communications10.1145/3103535.310353721:1(5-10)Online publication date: 31-May-2017
https://dl.acm.org/doi/10.1145/3103535.3103537
Kuo CChien LLu YSuen CAghdam AGuo MHong JNadimi E(2013)Scheduling algorithm with energy-response trade-off considerations for mixed task setsProceedings of the 2013 Research in Adaptive and Convergent Systems10.1145/2513228.2513236(410-415)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2513228.2513236
Kremer U(2009)Low-Power/Energy Compiler OptimizationsLow-Power Processors and Systems on Chips10.1201/9781420037203.ch18(18-1-18-8)Online publication date: 4-Dec-2009
https://doi.org/10.1201/9781420037203.ch18
Kremer U(2007)Compilation Techniques for Power, Energy, and Thermal ManagementDesigning Embedded Processors10.1007/978-1-4020-5869-1_13(287-303)Online publication date: 2007
https://doi.org/10.1007/978-1-4020-5869-1_13
Martin TSiewiorek D(2003)Nonideal Battery Properties and Their Impact on Software Design for Wearable ComputersIEEE Transactions on Computers10.1109/TC.2003.122363252:8(979-984)Online publication date: 1-Aug-2003
https://dl.acm.org/doi/10.1109/TC.2003.1223632
Viredaz MWallach D(2003)Power Evaluation of a Handheld ComputerIEEE Micro10.1109/MM.2003.117990023:1(66-74)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.1109/MM.2003.1179900
Park SSrivastava MBhattacharyya SMudge TWolf WJerraya A(2002)Dynamic battery state aware approaches for improving battery utilizationProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581666(225-231)Online publication date: 8-Oct-2002
https://dl.acm.org/doi/10.1145/581630.581666
Benini LMicheli G(2002)Logic Synthesis for Low PowerLogic Synthesis and Verification10.1007/978-1-4615-0817-5_8(197-223)Online publication date: 2002
https://doi.org/10.1007/978-1-4615-0817-5_8
Rakhmatov DVrudhula SErnst R(2001)An analytical high-level battery model for use in energy management of portable electronic systemsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603196(488-493)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603196
Jha NErnst R(2001)Low power system scheduling and synthesisProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603147(259-263)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603147
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