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Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

Published: 08 March 2018 Publication History

Abstract

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 102 (104) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

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  • (2021)EXIT Analysis of Interleaver Division Multiple Access System with LDPC CodeIOP Conference Series: Earth and Environmental Science10.1088/1755-1315/693/1/012059693:1(012059)Online publication date: 1-Mar-2021
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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 14, Issue 1
January 2018
289 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/3143783
  • Editor:
  • Yuan Xie
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 08 March 2018
Accepted: 01 October 2017
Revised: 01 July 2017
Received: 01 April 2017
Published in JETC Volume 14, Issue 1

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Author Tags

  1. Spin-transfer torque random access memory (STT-RAM)
  2. asymmetric log-likelihood ratio (A-LLR)
  3. channel model
  4. low-density parity-check (LDPC) code
  5. reliability
  6. semi-random parity check matrix

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Funding Sources

  • National Natural Science Foundation of China NSFC
  • new strategic industries development projects of Shenzhen City

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Cited By

View all
  • (2021)EXIT Analysis of Interleaver Division Multiple Access System with LDPC CodeIOP Conference Series: Earth and Environmental Science10.1088/1755-1315/693/1/012059693:1(012059)Online publication date: 1-Mar-2021
  • (2020)Robust Unsupervised Cross-modal Hashing for Multimedia RetrievalACM Transactions on Information Systems10.1145/338954738:3(1-25)Online publication date: 5-Jun-2020
  • (2019)Study on Data Analysis of Assessment in Class Based on Students' Evaluation of TeachingProceedings of the 2019 International Conference on Big Data and Education10.1145/3322134.3322138(103-107)Online publication date: 30-Mar-2019

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