research-article

Characterizing 3D Floating Gate NAND Flash: Observations, Analyses, and Implications

Authors:

Changsheng Xie,

Ping HuangAuthors Info & Claims

ACM Transactions on Storage (TOS), Volume 14, Issue 2

Article No.: 16, Pages 1 - 31

https://doi.org/10.1145/3162616

Published: 12 April 2018 Publication History

Abstract

As both NAND flash memory manufacturers and users are turning their attentions from planar architecture towards three-dimensional (3D) architecture, it becomes critical and urgent to understand the characteristics of 3D NAND flash memory. These characteristics, especially those different from planar NAND flash, can significantly affect design choices of flash management techniques. In this article, we present a characterization study on the state-of-the-art 3D floating gate (FG) NAND flash memory through comprehensive experiments on an FPGA-based 3D NAND flash evaluation platform. We make distinct observations on its performance and reliability, such as operation latencies and various error patterns, followed by careful analyses from physical and circuit-level perspectives. Although 3D FG NAND flash provides much higher storage densities than planar NAND flash, it faces new performance challenges of garbage collection overhead and program performance variations and more complicated reliability issues due to, e.g., distinct location dependence and value dependence of errors. We also summarize the differences between 3D FG NAND flash and planar NAND flash and discuss implications on the designs of NAND flash management techniques brought by the architecture innovation. We believe that our work will facilitate developing novel 3D FG NAND flash-oriented designs to achieve better performance and reliability.

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Tian HTang JLi JSha ZYang FCai ZLiao J(2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 16-Apr-2024
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Zhang MWu FYu QXie C(2024)PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND FlashIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.334619024:1(49-58)Online publication date: Mar-2024
https://doi.org/10.1109/TDMR.2023.3346190
Feng HWei DGu SPiao ZWang YQiao L(2024)Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash PerformanceIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.336690271:5(2372-2383)Online publication date: May-2024
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Index Terms

Characterizing 3D Floating Gate NAND Flash: Observations, Analyses, and Implications
1. General and reference
  1. Cross-computing tools and techniques
2. Hardware
  1. Emerging technologies
    1. Memory and dense storage
  2. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory

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Published In

cover image ACM Transactions on Storage

ACM Transactions on Storage Volume 14, Issue 2

May 2018

210 pages

ISSN:1553-3077

EISSN:1553-3093

DOI:10.1145/3208078

Editor:
Sam H. Noh
Ulsan National Institute of Science and Technology, Ulsan, Korea

Issue’s Table of Contents

Copyright © 2018 ACM.

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Association for Computing Machinery

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Publication History

Published: 12 April 2018

Accepted: 01 November 2017

Revised: 01 September 2017

Received: 01 June 2017

Published in TOS Volume 14, Issue 2

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Shenzhen Basic Research Project
National Natural Science Foundation of China
111 Project
Wuhan Science and Technology Project
Fundamental Research Funds for the Central Universities

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Cited By

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https://dl.acm.org/doi/10.1145/3659101
Zhang MWu FYu QXie C(2024)PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND FlashIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.334619024:1(49-58)Online publication date: Mar-2024
https://doi.org/10.1109/TDMR.2023.3346190
Feng HWei DGu SPiao ZWang YQiao L(2024)Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash PerformanceIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.336690271:5(2372-2383)Online publication date: May-2024
https://doi.org/10.1109/TCSI.2024.3366902
Pang SDeng YZhang GHuang JWu Z(2024)Minato: A Read-Disturb-Aware Dynamic Buffer Management Scheme for NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336410943:7(1930-1943)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2024.3364109
Wang HGuan ZLi JLuo ZDu XWang ZZhao HShen SYin YLi X(2024) Silicon‐Compatible Ferroelectric Tunnel Junctions with a SiO 2 /Hf 0.5 Zr 0.5 O 2 Composite Barrier as Low‐Voltage and Ultra‐High‐Speed Memristors Advanced Materials10.1002/adma.20221130536:15Online publication date: 7-Feb-2024
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Li YHan GHuang SLiu CZhang MWu F(2023)Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash MemoryIEEE Transactions on Consumer Electronics10.1109/TCE.2022.321358569:1(9-17)Online publication date: Mar-2023
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Li YHan GLiu CZhang MWu F(2023)Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D nand Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.329707042:12(5146-5150)Online publication date: 1-Dec-2023
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Du YGao YHuang SLi Q(2023)LDPC Level Prediction Toward Read Performance of High-Density Flash MemoriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.323884542:10(3264-3274)Online publication date: 30-Jan-2023
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Cui JZeng ZHuang JYuan WYang L(2023)Improving 3-D NAND SSD Read Performance by Parallelizing Read-RetryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319125642:3(768-780)Online publication date: 1-Mar-2023
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