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EXTRA: an open platform for reconfigurable architectures

Authors:

Cătălin Bogdan Ciobanu,

Giulio Stramondo,

Ana Lucia Varbanescu,

Andreas Brokalakis,

Antonis Nikitakis,

Lorenzo Di Tucci,

Luca Stornaiuolo,

Marco Santambrogio,

Grigorios Chrysos,

Charalampos Vatsolakis,

Charitopoulos Georgios, and

Dionisios PnevmatikatosAuthors Info & Claims

SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

July 2018

Pages 220 - 229

https://doi.org/10.1145/3229631.3236092

Published: 15 July 2018 Publication History

Abstract

Reconfigurable hardware is becoming increasingly mainstream, evolving to a valid alternative to Graphics Processing Units-based hardware accelerators. However, several major challenges remain for migrating existing software to heterogeneous reconfigurable architectures. The EXTRA project aims to develop an integrated environment for developing and programming reconfigurable architectures. The EXTRA platform enables the joint optimization of architecture, tools, and reconfiguration technology, and targets the future High Performance Computing hardware nodes. In this paper, we present four innovative EXTRA technologies: (1) a hardware-software co-design framework; (2) a parallel memory system; (3) a decoupled access execute framework for reconfigurable technology; and (4) transparent access and virtualization of reconfigurable hardware accelerators. Moreover, we describe how the EXTRA technologies targeting the Amazon F1 cloud compute instances can be used in medical applications such as the retinal image segmentation.

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Cited By

Stornaiuolo LRabozzi MSantambrogio MSciuto DCiobanu CStramondo GVarbanescu A(2019)Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLSVLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms10.1007/978-3-030-23425-6_4(53-78)Online publication date: 26-Jun-2019
https://doi.org/10.1007/978-3-030-23425-6_4
Stornaiuolo LRabozzi MSciuto DSantambrogio MStramondo GCiobanu CVarbanescu A(2018)HLS Support for Polymorphic Parallel Memories2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2018.8644899(143-148)Online publication date: Oct-2018
https://doi.org/10.1109/VLSI-SoC.2018.8644899

Index Terms

EXTRA: an open platform for reconfigurable architectures
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Data flow architectures
      2. Reconfigurable computing
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Hardware-software codesign
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators

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Published In

cover image ACM Other conferences

SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

July 2018

263 pages

ISBN:9781450364942

DOI:10.1145/3229631

General Chair:
Trevor Mudge
University of Michigan - Ann Arbor
,
Program Chair:
Dionisios N. Pnevmatikatos
Technical University of Crete and ICS - FORTH, Greece

Copyright © 2018 Owner/Author.

This work is licensed under a Creative Commons Attribution-ShareAlike International 4.0 License.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 July 2018

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Horizon 2020 Framework Programme

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SAMOS XVIII

SAMOS XVIII: Architectures, Modeling, and Simulation

July 15 - 19, 2018

Pythagorion, Greece

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Cited By

Stornaiuolo LRabozzi MSantambrogio MSciuto DCiobanu CStramondo GVarbanescu A(2019)Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLSVLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms10.1007/978-3-030-23425-6_4(53-78)Online publication date: 26-Jun-2019
https://doi.org/10.1007/978-3-030-23425-6_4
Stornaiuolo LRabozzi MSciuto DSantambrogio MStramondo GCiobanu CVarbanescu A(2018)HLS Support for Polymorphic Parallel Memories2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2018.8644899(143-148)Online publication date: Oct-2018
https://doi.org/10.1109/VLSI-SoC.2018.8644899

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