research-article

Vulnerability-Tolerant Secure Architectures

Authors:

Valeria Bertacco,

Mohit TiwariAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 5

https://doi.org/10.1145/3240765.3240769

Published: 05 November 2018 Publication History

Abstract

Today, secure systems are built by identifying potential vulnerabilities and then adding protections to thwart the associated attacks. Unfortunately, the complexity of today's systems makes it impossible to prove that all attacks are stopped, so clever attackers find a way around even the most carefully designed protections. In this article, we take a sobering look at the state of secure system design, and ask ourselves why the “security arms race” never ends? The answer lies in our inability to develop adequate security verification technologies. We then examine an advanced defensive system in nature – the human immune system – and we discover that it does not remove vulnerabilities, rather it adds offensive measures to protect the body when its vulnerabilities are penetrated We close the article with brief speculation on how the human immune system could inspire more capable secure system designs.

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Vulnerability-Tolerant Secure Architectures

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cover image Guide Proceedings

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

Copyright © 2018.

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IEEE Press

Publication History

Published: 05 November 2018

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Cited By

Guan WTang XLu HTan JWang JZhang YZhang Y(2025)LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQNIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343601344:2(709-722)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3436013
Guan WTang XLu HTan JWang JZhang Y(2024)Transformer-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DTQN2024 IEEE 42nd International Conference on Computer Design (ICCD)10.1109/ICCD63220.2024.00030(134-143)Online publication date: 18-Nov-2024
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Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Kai SPui CWang FJiang SWang BHuang YHao J(2023)TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137175(1-5)Online publication date: Apr-2023
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Molter MKumar RKoller SBhatti OAmbasana NRosenbaum ESwaminathan M(2023)Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)10.1109/ECTC51909.2023.00160(935-942)Online publication date: May-2023
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Meitei NBaishnab KTrivedi G(2023)Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithmInternational Journal of Circuit Theory and Applications10.1002/cta.367251:10(4879-4896)Online publication date: 29-May-2023
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Amini MZhang ZPenmetsa SZhang YHao JLiu WZhang ARangwala H(2022)Generalizable Floorplanner through Corner Block List Representation and Hypergraph EmbeddingProceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining10.1145/3534678.3539220(2692-2702)Online publication date: 14-Aug-2022
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