research-article

An Efficient Data Reuse Strategy for Multi-Pattern Data Access

Authors:

Dian ZhouAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/3240765.3240778

Published: 05 November 2018 Publication History

Abstract

Memory partitioning has been widely adopted to increase the memory bandwidth. Data reuse is a hardware-efficient way to improve data access throughput by exploiting locality in memory access patterns. We found that for many applications in image and video processing, a global data reuse scheme can be shared by multiple patterns. In this paper, we propose an efficient data reuse strategy for multi-pattern data access. Firstly, a heuristic algorithm is proposed to extract the reuse information as well as find the non-reusable data elements of each pattern. Then the non-reusable elements are partitioned into several memory banks by an efficient memory partitioning algorithm. Moreover, the reuse information is utilized to generate the global data reuse logic shared by the multi-pattern. We design a novel algorithm to minimize the number of registers required by the data reuse logic. Experimental results show that compared with the state-of-the-art approach, our proposed method can reduce the number of required BRAMs by 62.2% on average, with the average reduction of 82.1% in SLICE, 87.1% in LUTs, 71.6% in Flip-Flops, 73.1% in DSP48Es, 83.8% in SRLs, 46.7% in storage overhead, 79.1% in dynamic power consumption, and 82.6% in execution time of memory partitioning. Besides, the performance is improved by 14.4%.

References

[1]

2018. Bicubic interpolation. Retrieved March 7, 2018 from https://www.mpi-hd.mpg.de/astrophysik/HEA/1600.html

[2]

2018. Xilinx Virtex-7 VC707 Evaluation Kit. Retrieved March 1, 2018 from http://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html

[3]

2018. Xilinx Vivado Design Suite 2016.4. Retrieved March 1, 2018 from http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2016-4.html

[4]

Yosi Ben Asher and Nadav Rotem. 2010. Automatic memory partitioning: increasing memory parallelism via data structure partitioning. In Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. 155–162.

[5]

J. Cong, W. Jiang, B. Liu, and Y. Zou. 2011. Automatic memory partitioning and scheduling for throughput and power optimization. ACM Transaction on Design Automation of Electronic Systems (TODAES) 16 (2011).

[6]

J. Cong, V. Sarkar, G. Reinman, and A. Bui. 2011. Customizable domain-specific computing. In IEEE Design and Test of Computers. 5–15.

[7]

Juan Escobedo and Mingjie Lin. 2016. Tessellation-Based Multi-Block Memory Mapping Scheme for High-Level Synthesis with FPGA. In 2016 International Conference on Field-Programmable Technology (FPT). IEEE, 125–132.

[8]

P. Li, Y. Wang, P. Zhang, G. Luo, T. Wang, and J. Cong. 2012. Memory partitioning and scheduling co-optimization in behavioral synthesis. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 488–495.

[9]

C. Meng, S. Yin, P. Ouyang, L. Liu, and S. Wei. 2015. Efficient memory partitioning for parallel data access in multidimensional arrays. In Proceedings of the 52th Annual Design Automation Conference (DAC).

[10]

J.M.S. Prewitt. 1970. Picture processing and psychopictorics. Academic Press.

[11]

J. Su, F. Yang, X. Zeng, and D. Zhou. 2016. Efficient memory partitioning for parallel data access via data reuse. In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). 138–147.

[12]

D.T.W., Bruce Jacob, and Spencer W. Ng. 2008. Memory Systems - Cache, DRAM, Disk. Denise E.M. Penrose.

[13]

Y. Wang, P. Li, and J. Cong. 2014. Theory and algorithm for generalized memory partitioning in high-level synthesis. In Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA).

[14]

Y. Wang, P. Li, P. Zhang, C. Zhang, and J. Cong. 2013. Memory partitioning for multidimensional arrays in high-level synthesis. In Proceedings of the 50th Annual Design Automation Conference (DAC).

[15]

Y. Wang, P. Zhang, X. Cheng, and J. Cong. 2012. An integrated and automated memory optimization flow for FPGA behavioral synthesis. In Asia and South Pacific Design Automation Conf (ASP-DAC). 257–262.

[16]

Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, and Shaojun Wei. 2016. Multibank memory optimization for parallel data access in multiple data arrays. In Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD). ACM, 32:1–32:8.

[17]

Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, and Shaojun Wei. 2017. Memory partitioning for parallel multi-pattern data access in multiple data arrays. “IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems” (2017).

[18]

Shouyi Yin, Zhicong Xie, and Shaojun Wei. 2017. Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 1–6.

[19]

Yuan Zhou, Khalid Al-Hawaj, and Zhiru Zhang. 2017. A new approach to automatic memory banking using trace-baced address mining. In Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). 179–188.

Cited By

Lin MEscobedo J(2020)FPGA Memory Optimization in High-Level SynthesisFPGA Algorithms and Applications for the Internet of Things10.4018/978-1-5225-9806-0.ch003(51-81)Online publication date: 30-Mar-2020
https://doi.org/10.4018/978-1-5225-9806-0.ch003
Liu BYang FZhou DZeng X(2020)An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9181278(1-4)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9181278
Csordas GAsiatici MIenne P(2019)In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00030(188-196)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00030

Index Terms

An Efficient Data Reuse Strategy for Multi-Pattern Data Access
1. Hardware
  1. Electronic design automation
  2. Integrated circuits
    1. Semiconductor memory

Index terms have been assigned to the content through auto-classification.

Recommendations

Efficient Memory Partitioning for Parallel Data Access via Data Reuse
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

In this paper, we propose an efficient memory partitioning algorithm for parallel data access via data reuse. We found that for most of the applications in image and video processing, a large amount of data can be reused among different iterations in a ...
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse

Memory bandwidth has become a bottleneck that impedes performance improvement during the parallelism optimization of the datapath. Memory partitioning is a practical approach to reduce bank-level conflicts and increase the bandwidth on a field-...
Energy-efficient multi-level cell phase-change memory system with data encoding
ICCD '11: Proceedings of the 2011 IEEE 29th International Conference on Computer Design

Phase-change memory (PCM) is one of the most promising technologies among emerging non-volatile memories. Recently, the technology of multi-level cell (MLC) for PCM has been developed and a high capacity memory system can be implemented by storing ...

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

Copyright © 2018.

Publisher

IEEE Press

Publication History

Published: 05 November 2018

Permissions

Request permissions for this article.

Request Permissions

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
118
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Lin MEscobedo J(2020)FPGA Memory Optimization in High-Level SynthesisFPGA Algorithms and Applications for the Internet of Things10.4018/978-1-5225-9806-0.ch003(51-81)Online publication date: 30-Mar-2020
https://doi.org/10.4018/978-1-5225-9806-0.ch003
Liu BYang FZhou DZeng X(2020)An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9181278(1-4)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9181278
Csordas GAsiatici MIenne P(2019)In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00030(188-196)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00030

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents