research-article

ReRAM-based processing-in-memory architecture for blockchain platforms

Authors:

Zili ShaoAuthors Info & Claims

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

Pages 615 - 620

https://doi.org/10.1145/3287624.3287656

Published: 21 January 2019 Publication History

Abstract

Blockchain's decentralized and consensus mechanism has attracted lots of applications, such as IoT devices. Blockchain maintains a linked list of blocks and grows by mining new blocks. However, the Blockchain mining consumes huge computation resource and energy, which is unacceptable for resource-limited embedded devices. This paper for the first time presents a ReRAM-based processing-in-memory architecture for Blockchain mining, called Re-Mining. Re-Mining includes a message schedule module and a SHA computation module. The modules are composed of several basic ReRAM-based logic operations units, such as ROR, RSF and XOR. Re-Mining further designs intra-transaction and inter-transaction parallel mechanisms to accelerate the Blockchain mining. Simulation results show that the proposed Re-Mining architecture outperforms CPU-based and GPU-based implementations significantly.

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Cited By

Wang TChen ZZhu WWei QShen ZShao Z(2024)A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330139343:1(85-98)Online publication date: Jan-2024
https://doi.org/10.1109/TCAD.2023.3301393
Chen F(2024)System Support for Environmentally Sustainable Computing in Data Centers2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00094(490-495)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00094
Goswami BSuri MTeuscher CHan J(2022)Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM CrossbarProceedings of the 17th ACM International Symposium on Nanoscale Architectures10.1145/3565478.3572329(1-6)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3565478.3572329
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cover image ACM Conferences

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

January 2019

794 pages

ISBN:9781450360074

DOI:10.1145/3287624

General Chair:
Toshiyuki Shibuya
Fujitsu Laboratories

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEEE CAS
IEEE CEDA
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

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ASPDAC '19: 24th Asia and South Pacific Design Automation Conference

January 21 - 24, 2019

Tokyo, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Cited By

Wang TChen ZZhu WWei QShen ZShao Z(2024)A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330139343:1(85-98)Online publication date: Jan-2024
https://doi.org/10.1109/TCAD.2023.3301393
Chen F(2024)System Support for Environmentally Sustainable Computing in Data Centers2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00094(490-495)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00094
Goswami BSuri MTeuscher CHan J(2022)Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM CrossbarProceedings of the 17th ACM International Symposium on Nanoscale Architectures10.1145/3565478.3572329(1-6)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3565478.3572329
Wang TShen ZShao ZGrosser TLee K(2022)Co-mining: a processing-in-memory assisted framework for memory-intensive PoW accelerationProceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3519941.3535064(1-12)Online publication date: 14-Jun-2022
https://dl.acm.org/doi/10.1145/3519941.3535064
Wei QShen ZTong YJia ZJu LChen JLi BMitra TYoung EXiong J(2022)Re-LSMProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549392(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549392
Liu YQian KWang KHe L(2022)Effective Scaling of Blockchain Beyond Consensus Innovations and Moore’s Law: Challenges and OpportunitiesIEEE Systems Journal10.1109/JSYST.2021.308779816:1(1424-1435)Online publication date: Mar-2022
https://doi.org/10.1109/JSYST.2021.3087798
Oliveira GBoroumand AGhose SGomez-Luna JMutlu O(2022)Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI54635.2022.00060(273-278)Online publication date: Jul-2022
https://doi.org/10.1109/ISVLSI54635.2022.00060
Garzón EYavits LLanuzza MTeman AWebster J(2022)Emerging Memory Structures for VLSI CircuitsWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W8438(1-28)Online publication date: 12-May-2022
https://doi.org/10.1002/047134608X.W8438
Wang FSun GLuo G(2021)SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643493(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643493
Zhang YLiu BJia ZChen RShen Z(2021)An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVCJournal of Systems Architecture10.1016/j.sysarc.2021.102123(102123)Online publication date: Apr-2021
https://doi.org/10.1016/j.sysarc.2021.102123
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