research-article

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks

Authors:

Kun-Han (Hans) Tsai,

Wu-Tung ChengAuthors Info & Claims

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

Pages 341 - 346

https://doi.org/10.1145/3287624.3287692

Published: 21 January 2019 Publication History

Abstract

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

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Digital Library

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Cited By

Zeng YCui X(2024)A High Performance PODEM Algorithm with the Improved Backtrace Process2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661307(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661307
Yun HLim HLee HYoon DKang S(2024)An Efficient Scan Diagnosis for Intermittent Faults Using CNN With Multi-Channel DataIEEE Access10.1109/ACCESS.2024.347522912(146463-146475)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3475229
Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
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cover image ACM Conferences

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

January 2019

794 pages

ISBN:9781450360074

DOI:10.1145/3287624

General Chair:
Toshiyuki Shibuya
Fujitsu Laboratories

Copyright © 2019 ACM.

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IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEEE CAS
IEEE CEDA
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

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Published: 21 January 2019

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ASPDAC '19: 24th Asia and South Pacific Design Automation Conference

January 21 - 24, 2019

Tokyo, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Cited By

Zeng YCui X(2024)A High Performance PODEM Algorithm with the Improved Backtrace Process2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661307(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661307
Yun HLim HLee HYoon DKang S(2024)An Efficient Scan Diagnosis for Intermittent Faults Using CNN With Multi-Channel DataIEEE Access10.1109/ACCESS.2024.347522912(146463-146475)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3475229
Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
Kim SJang SKang S(2023)Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault DiagnosisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322489942:8(2717-2727)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3224899
Zhao ZCai Z(2023)A Review of Intelligent Design for Test Based on Machine Learning2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218713(116-120)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218713
Amuru DZahra AVudumula HCherupally PGurram SAhmad AAbbas Z(2023)AI/ML algorithms and applications in VLSI design and technologyIntegration, the VLSI Journal10.1016/j.vlsi.2023.06.00293:COnline publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1016/j.vlsi.2023.06.002
Sun YMillican S(2022)Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point InsertionJournal of Electronic Testing10.1007/s10836-022-06016-938:4(339-352)Online publication date: 4-Aug-2022
https://doi.org/10.1007/s10836-022-06016-9
Roy SMillican SAgrawal V(2021)Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits2021 IEEE 39th VLSI Test Symposium (VTS)10.1109/VTS50974.2021.9441051(1-14)Online publication date: 25-Apr-2021
https://doi.org/10.1109/VTS50974.2021.9441051
Roy SMillican SAgrawal V(2021)Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)10.1109/VLSID51830.2021.00059(316-321)Online publication date: Feb-2021
https://doi.org/10.1109/VLSID51830.2021.00059
Lim HCheong MKang S(2020)Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor NetworksSensors10.3390/s2017477120:17(4771)Online publication date: 24-Aug-2020
https://doi.org/10.3390/s20174771
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