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Managing application parallelism via parallel efficiency regulation: poster

Published: 16 February 2019 Publication History
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  • Abstract

    Modern multiprocessor systems contain a wealth of compute, memory, and communication network resources, such that multiple applications can often successfully execute on and compete for these resources. Unfortunately, good performance for individual applications in addition to achieving overall system efficiency proves a difficult task, especially for applications with low parallel efficiency (speedup per utilized computational core). Limitations to parallel efficiency arise out of factors such as algorithm design, excess synchronization, limitations in hardware resources, and sub-optimal task placement on CPUs.
    In this work, we introduce MAPPER, a Manager of Application Parallelism via Parallel Efficiency Regulation. MAPPER monitors and coordinates all participating applications by making two coupled decisions: how much parallelism to afford to each application, and which specific CPU cores to schedule applications on. While MAPPER can work for generic applications without modifying their parallel runtimes, we introduce a simple interface that can be used by parallel runtime systems for a tighter integration, resulting in better task granularity control. Using MAPPER can result in up to 3.3X speedup, with an average performance improvement of 20%.

    References

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    Christian Bienia. 2011. Benchmarking Modern Multiprocessors. Ph.D. Dissertation. Princeton University.
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    A. J. Dorta, C. Rodriguez, and F. de Sande. 2005. The OpenMP source code repository. In 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing. 244--250.
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    Sharanyan Srikanthan, Sandhya Dwarkadas, and Kai Shen. 2015. Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems. In 2015 USENIX Annual Technical Conference (USENIX ATC 15). USENIX Association, 529--540.
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    Sharanyan Srikanthan, Sandhya Dwarkadas, and Kai Shen. 2016. Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing. In 2016 USENIX Annual Technical Conference (USENIX ATC 16). USENIX Association, 323--336.

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    cover image ACM Conferences
    PPoPP '19: Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming
    February 2019
    472 pages
    ISBN:9781450362252
    DOI:10.1145/3293883
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    New York, NY, United States

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    Published: 16 February 2019

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    PPoPP '19 Paper Acceptance Rate 29 of 152 submissions, 19%;
    Overall Acceptance Rate 230 of 1,014 submissions, 23%

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