research-article

Hardware Acceleration of Image Registration Algorithm on FPGA-based Systems on Chip

Authors:

Ioannis Stratakos,

Dimitrios Gourounas,

Vasileios Tsoutsouras,

Theodore Economopoulos,

George Matsopoulos,

Dimitrios SoudrisAuthors Info & Claims

COINS '19: Proceedings of the International Conference on Omni-Layer Intelligent Systems

Pages 92 - 97

https://doi.org/10.1145/3312614.3312636

Published: 05 May 2019 Publication History

Abstract

Image processing algorithms are dominating contemporary digital systems due to their importance and adoption by a large number of application domains. Despite their significance, their computational requirements often limit their usage, especially in deeply embedded designs. Heterogeneous computing systems offer a promising solution for this performance gap, leading to their ever increasing utilization by designers. This work targets the acceleration of an image registration pipeline on a System-on-Chip (SoC) including both general purpose and re-configurable computing elements. The evaluation of our proposed HW/SW co-designed image registration application on a state-of-the-art FPGA based SoC showcases its ability to outperform software designs leading to orders of performance speedup (up to 67x) against embedded CPUs.

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Cited By

Sorrentino GVenere MConficconi DD’Arnese ESantambrogio M(2023) Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable ArchitecturesACM Transactions on Embedded Computing Systems10.1145/360792822:5s(1-24)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3607928
D'Arnese EConficconi DSozzo EFusco LSciuto DSantambrogio M(2023)Faber: A Hardware/SoftWare Toolchain for Image RegistrationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.321889834:1(291-303)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TPDS.2022.3218898
Zeni ADel Sozzo ED'Arnese EConficconi DSantambrogio M(2023)Starlight: A kernel optimizer for GPU processingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104832(104832)Online publication date: Dec-2023
https://doi.org/10.1016/j.jpdc.2023.104832
Show More Cited By

Index Terms

Hardware Acceleration of Image Registration Algorithm on FPGA-based Systems on Chip
1. Computing methodologies
  1. Computer graphics
    1. Image manipulation
      1. Image processing
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Hardware-software codesign
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators

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cover image ACM Other conferences

COINS '19: Proceedings of the International Conference on Omni-Layer Intelligent Systems

May 2019

241 pages

ISBN:9781450366403

DOI:10.1145/3312614

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 May 2019

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COINS '19

COINS '19: INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS

May 5 - 7, 2019

Crete, Greece

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Cited By

Sorrentino GVenere MConficconi DD’Arnese ESantambrogio M(2023) Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable ArchitecturesACM Transactions on Embedded Computing Systems10.1145/360792822:5s(1-24)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3607928
D'Arnese EConficconi DSozzo EFusco LSciuto DSantambrogio M(2023)Faber: A Hardware/SoftWare Toolchain for Image RegistrationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.321889834:1(291-303)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TPDS.2022.3218898
Zeni ADel Sozzo ED'Arnese EConficconi DSantambrogio M(2023)Starlight: A kernel optimizer for GPU processingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104832(104832)Online publication date: Dec-2023
https://doi.org/10.1016/j.jpdc.2023.104832
Krainyk Y(2023)Design and Implementation of Image Sensor Data Capture Based on FPGASN Computer Science10.1007/s42979-023-02433-55:1Online publication date: 8-Dec-2023
https://dl.acm.org/doi/10.1007/s42979-023-02433-5
Conficconi DD'Arnese EDel Sozzo ESciuto DSantambrogio MShannon LAdler M(2021)A Framework for Customizable FPGA-based Image Registration AcceleratorsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439291(251-261)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439291
Kehagias DJankovic MSiavvas MGelenbe E(2021)Investigating the Interaction between Energy Consumption, Quality of Service, Reliability, Security, and Maintainability of Computer Systems and NetworksSN Computer Science10.1007/s42979-020-00404-82:1Online publication date: 8-Jan-2021
https://doi.org/10.1007/s42979-020-00404-8
Chen CQu XGao L(2019)An FPGA-based implementation of Fourier-Mellin Transform2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP)10.1109/ICSIDP47821.2019.9173044(1-6)Online publication date: Dec-2019
https://doi.org/10.1109/ICSIDP47821.2019.9173044

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