research-article

Open access

An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM

Authors:

Laurens van Dam,

Johan Peltenburg,

H. Peter HofsteeAuthors Info & Claims

CoNGA'19: Proceedings of the Conference for Next Generation Arithmetic 2019

Article No.: 5, Pages 1 - 10

https://doi.org/10.1145/3316279.3316284

Published: 13 March 2019 Publication History

Abstract

The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 106 elements, a hardware speedup of approximately 104 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 105 to 106. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.

References

[1]

Boost. 2013. cpp_dec_float - 1.63.0. http://www.boost.org/doc/libs/1_63_0/libs/multiprecision/doc/html/boost_multiprecision/tut/floats/cpp_dec_float.html. (2013). {Online; accessed 2018-11-20}.

[2]

Jianyu Chen, Zaid Al-Ars, and H. Peter Hofstee. 2018. A Matrix-multiply Unit for Posits in Reconfigurable Logic Leveraging (Open)CAPI. In Proceedings of the Conference for Next Generation Arithmetic. ACM, Singapore, 1:1--1:5.

Digital Library

[3]

Richard Durbin, Sean Eddy, Anders Krogh, and Graeme Mitchison. 1998. Biological Sequence Analysis: Probabilistic Models of Proteins and Nucleic Acids (1 ed.). Cambridge University Press.

[4]

John L Gustafson. 2015. The End of Error: Unum Computing. CRC Press.

[5]

John L. Gustafson. 2017. Posit Arithmetic. https://posithub.org/docs/Posits4.pdf

[6]

John L. Gustafson and Isaac T. Yonemoto. 2017. Beating Floating Point at its Own Game: Posit Arithmetic. Supercomputing Frontiers and Innovations 4, 2 (April 2017), 71--86.

Digital Library

[7]

Reinhard Kirchner and Ulrich Kulisch. 1988. Arithmetic for vector processors. In Reliability in Computing. Elsevier, 3--41.

Digital Library

[8]

Jack Koenig, David Biancolin, Jonathan Bachrach, and Krste Asanovic. 2017. A Hardware Accelerator for Computing an Exact Dot Product. In Computer Arithmetic (ARITH), 2017 IEEE 24th Symposium on. IEEE, 114--121.

[9]

Aaron McKenna, Matthew Hanna, Eric Banks, Andrey Sivachenko, Kristian Cibulskis, Andrew Kernytsky, Kiran Garimella, David Altshuler, Stacey Gabriel, Mark Daly, et al. 2010. The Genome Analysis Toolkit: a MapReduce framework for analyzing next-generation DNA sequencing data. Genome research (2010).

[10]

R. K. Montoye, E. Hokenek, and S. L. Runyon. 1990. Design of the IBM RISC System/6000 Floating-point Execution Unit. IBM J. Res. Dev. 34, 1 (Jan. 1990), 59--70.

Digital Library

[11]

Johan Peltenburg. 2018. fletcher: A framework to integrate FPGA accelerators with Apache Arrow. (2018). https://github.com/johanpel/fletcher

[12]

J. Peltenburg, S. Ren, and Z. Al-Ars. 2016. Maximizing systolic array efficiency to accelerate the PairHMM Forward Algorithm. In 2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). 758--762.

[13]

Stillwater Supercomputing, Inc. 2017. universal: Universal Number Arithmetic. (2017). https://github.com/stillwater-sc/universal

[14]

Jeffrey Stuecheli, Bart Blaner, CR Johns, and MS Siegel. 2015. CAPI: A coherent accelerator processor interface. IBM Journal of Research and Development 59, 1 (2015), 7--1.

Digital Library

[15]

The Apache Software Foundation. 2016. Apache Arrow. (2016). https://arrow.apache.org

[16]

Laurens van Dam. 2018. Enabling High Performance Posit Arithmetic Applications Using Hardware Acceleration. Master's thesis. ISBN 978-94-6186-957-9.

Cited By

Shekhawat DGandhi JSantosh MPandey J(2023)PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic OperationsNext Generation Arithmetic10.1007/978-3-031-32180-1_6(88-100)Online publication date: 12-May-2023
https://doi.org/10.1007/978-3-031-32180-1_6
Cococcioni MRossi FRuffaldi ESaponara SDupont de Dinechin B(2021)Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and OpportunitiesIEEE Signal Processing Magazine10.1109/MSP.2020.298843638:1(97-110)Online publication date: Jan-2021
https://doi.org/10.1109/MSP.2020.2988436
Li EBanerjee SHuang SIyer RChen D(2021)Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment2021 IEEE 39th International Conference on Computer Design (ICCD)10.1109/ICCD53106.2021.00055(299-306)Online publication date: Oct-2021
https://doi.org/10.1109/ICCD53106.2021.00055
Show More Cited By

Recommendations

PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
Next Generation Arithmetic
Abstract
Arithmetic accelerators are always in demand for fast computations and logic operations. Here, posit arithmetic plays an important role; it outperforms the traditional IEEE-754 floating-point in terms of accuracy and dynamic range. This paper ...
Provably correct posit arithmetic with fixed-point big integer
CoNGA '18: Proceedings of the Conference for Next Generation Arithmetic

Floating-point number format is used extensively in many applications, especially scientific software. The applications rely on efficient hardware floating-point support to perform arithmetic operations. With the advent of multicore CPUs and massively ...
High-level .NET software implementations of unum type I and posit with simultaneous FPGA implementation using Hastlayer
CoNGA '18: Proceedings of the Conference for Next Generation Arithmetic

The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

CoNGA'19: Proceedings of the Conference for Next Generation Arithmetic 2019

March 2019

66 pages

ISBN:9781450371391

DOI:10.1145/3316279

General Chair:
John Gustafson
A*CRC, A*STAR Singapore, National University of Singapore
,
Program Chair:
Vassil Dimitrov
University of Calgary

Copyright © 2019 Owner/Author.

This work is licensed under a Creative Commons Attribution International 4.0 License.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 March 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

CoNGA'19

CoNGA'19: Conference for Next Generation Arithmetic 2019

March 13 - 14, 2019

Singapore, Singapore

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
671
Total Downloads

Downloads (Last 12 months)120
Downloads (Last 6 weeks)28

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Shekhawat DGandhi JSantosh MPandey J(2023)PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic OperationsNext Generation Arithmetic10.1007/978-3-031-32180-1_6(88-100)Online publication date: 12-May-2023
https://doi.org/10.1007/978-3-031-32180-1_6
Cococcioni MRossi FRuffaldi ESaponara SDupont de Dinechin B(2021)Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and OpportunitiesIEEE Signal Processing Magazine10.1109/MSP.2020.298843638:1(97-110)Online publication date: Jan-2021
https://doi.org/10.1109/MSP.2020.2988436
Li EBanerjee SHuang SIyer RChen D(2021)Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment2021 IEEE 39th International Conference on Computer Design (ICCD)10.1109/ICCD53106.2021.00055(299-306)Online publication date: Oct-2021
https://doi.org/10.1109/ICCD53106.2021.00055
Peltenburg Jvan Straten JBrobbel MAl-Ars ZHofstee H(2021)Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache ArrowJournal of Signal Processing Systems10.1007/s11265-021-01650-6Online publication date: 1-Mar-2021
https://doi.org/10.1007/s11265-021-01650-6
Murillo RDel Barrio ABotella G(2020)Customized Posit Adders and Multipliers using the FloPoCo Core Generator2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180771(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180771

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents