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Comprehensive Search for ECO Rectification Using Symbolic Sampling

Published: 02 June 2019 Publication History

Abstract

The task of an engineering change order (ECO) is to update the current implementation of a design according to its revised specification with minimum modification. Prior studies show that the amount of design modification majorly depends on the selection of rectification points, i.e., the input pins of gates whose functionality should be rectified with some patch circuitry. In realistic ECOs, as the netlist of the current implementation has been heavily optimized to meet design objectives, it is usually structurally dissimilar to the netlist of a revised specification, which is synthesized only by lightweight optimization. This paper proposes an ECO solution for optimized designs, which is robust against structural dissimilarity caused by design optimization. It locates candidate rectification points in a sampling domain, which significantly improves the scalability of rectification search. To synthesize the circuitry of patches, a structurally independent rewiring formulation is proposed to reuse existing logic in the implementation. Based on the proposed method, a newly developed engine is evaluated on the engineering changes arising in the design of microprocessors. Its ability to derive patches of superior quality is demonstrated in comparison to industrial tools.

References

[1]
E. Arbel, D. Geiger, V. N. Kravets, S. Krishnaswamy, R. Puri, and H. Ren. Logic modification synthesis. U.S. Patent 8,365,114, issued Jan. 29, 2013.
[2]
D. Brand, A. Drumm, S. Kundu, and P. Narain. Incremental synthesis. In Proc. ICCAD, pp. 14--18, 1994.
[3]
R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8):677--691, 1986.
[4]
W. Craig. Linear reasoning. A new form of the Herbrand-Gentzen theorem. The Journal of Symbolic Logic, 22(3): 250--268, 1957.
[5]
A.-Q. Dao, N.-Z. Lee, L.-C. Chen, M. P.-H. Lin, J.-H. R. Jiang, A. Mishchenko, and R. K. Brayton. Efficient computation of ECO patch functions. In Proc. DAC, pp. 51:1--51:6, 2018.
[6]
S.-Y. Huang, K.-C. Chen, and K.-T. Cheng. AutoFix: A hybrid tool for automatic logic rectification. IEEE Trans. CAD, 18(9): 1376--1384, 1999.
[7]
S.-L. Huang, W.-H. Lin, and C.-Y. Huang. Match and replace: A functional ECO engine for multi-error circuit rectification. IEEE Trans. CAD, 32(3): 467--478, 2013.
[8]
S. Krishnaswamy, H. Ren, N. Modi, and R. Puri. DeltaSyn: An efficient logic difference optimizer for ECO synthesis. In Proc. ICCAD, pp. 789--796, 2009.
[9]
J. C. Madre, O. Coudert, and J. P. Billon. Automating the diagnosis and the rectification of digital errors with PRIAM. In Proc. ICCAD, pp. 30--33, 1989.
[10]
N.-Z. Lee, V. N. Kravets, and J.-H. R. Jiang. Sequential engineering change order under retiming and resynthesis. In Proc. ICCAD, pp. 109--116, 2017.
[11]
I. Pomeranz and S. M. Reddy. On diagnosis and correction of design errors. In Proc. ICCAD, pp. 500--507, 1993.
[12]
H. Riener and G. Fey. Exact diagnosis using Boolean satisfiability. In Proc. ICCAD, pp. 53--58, 2016.
[13]
H. Riener, R. Ehlers, and G. Fey. CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. In Proc. ASP-DAC, pp. 251--256, 2017.
[14]
H. Ren, R. Puri, L. Reddy, S. Krishnaswamy, C. Washburn, J. Earl, and J. Keinert. Intuitive ECO synthesis for high performance circuits. In Proc. DATE, pp. 1002--1007, 2013.
[15]
A. Smith, A. G. Veneris, M. F. Ali, and A. Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. CAD, 24(10): 1606--1621, 2005.
[16]
N. Sörensson and N. Eén. Minisat v1. 13: A SAT solver with conflict- clause minimization. In Proc. SAT Competition, pp. 53--54, 2005.
[17]
K.-F. Tang, P.-K. Huang, C.-N. Chou, and C.-Y. Huang. Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. In Proc. DATE, pp. 1567--1572, 2012.
[18]
Y. Watanabe and R. K. Brayton. Incremental synthesis for engineering changes. In Proc. ICCD, pp. 40--43, 1991.
[19]
B.-H. Wu, C.-J. Yang, C.-Y. Huang, and J.-H. R. Jiang. A robust functional ECO engine by SAT proof minimization and interpolation techniques. In Proc. ICCAD, pp. 729--734, 2010.
[20]
H.-T. Zhang and J.-H. R. Jiang. Cost-aware patch generation for multi-target function rectification of engineering change orders. In Proc. DAC, pp. 96:1--96:6, 2018.

Cited By

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  • (2024)Selecting Rectification Targets for Patching Buggy Circuits2024 28th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT63601.2024.10705667(1-6)Online publication date: 1-Sep-2024
  • (2021)Algebraic Techniques for Rectification of Finite Field Circuits2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC53125.2021.9606976(1-6)Online publication date: 4-Oct-2021
  • (2021)Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424286(41-47)Online publication date: 7-Apr-2021
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cover image ACM Conferences
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
June 2019
1378 pages
ISBN:9781450367257
DOI:10.1145/3316781
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 June 2019

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Cited By

View all
  • (2024)Selecting Rectification Targets for Patching Buggy Circuits2024 28th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT63601.2024.10705667(1-6)Online publication date: 1-Sep-2024
  • (2021)Algebraic Techniques for Rectification of Finite Field Circuits2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC53125.2021.9606976(1-6)Online publication date: 4-Oct-2021
  • (2021)Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424286(41-47)Online publication date: 7-Apr-2021
  • (2021)Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques2021 IEEE 39th International Conference on Computer Design (ICCD)10.1109/ICCD53106.2021.00039(186-195)Online publication date: Oct-2021
  • (2020)Learning to automate the design updates from observed engineering changes in the chip development cycleProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408521(738-743)Online publication date: 9-Mar-2020
  • (2020)Exact DAG-aware rewritingProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408520(732-737)Online publication date: 9-Mar-2020
  • (2020)Engineering Change Order for Combinational and Sequential Design Rectification2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116504(726-731)Online publication date: Mar-2020
  • (2020)Exact DAG-Aware Rewriting2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116379(732-737)Online publication date: Mar-2020
  • (2020)Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116310(738-743)Online publication date: Mar-2020
  • (2020)Symbolic uniform sampling with XOR circuitsProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415616(1-9)Online publication date: 2-Nov-2020

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