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A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement)

Authors:

Chenglong Li,

Tao Li,

Junnan Li,

Hui Yang, and

Baosheng WangAuthors Info & Claims

SPAA '19: The 31st ACM Symposium on Parallelism in Algorithms and Architectures

June 2019

Pages 395 - 397

https://doi.org/10.1145/3323165.3323171

Published: 17 June 2019 Publication History

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Abstract

The high-performance hardware architectures for multi-field packet classification have been studied over the past decade. Although many FPGA-based solutions can achieve very high throughput, the limited FPGA resources severely hinders the scalability of the rulesets or matching fields. To address this issue, we present a parallel architecture named Wildcard-removed Two-dimensional Pipeline (WeeTP) to save memory usage of wildcards and reduce logic resources. WeeTP uses the Maximum Wildcard Overlap (MWO) algorithm to maximize the compression percentage by rearranging the ruleset. We implement and evaluate WeeTP on an Intel STRATIX V FPGA. Experimental results show that our approach can save 37% and 41% memory consumption on average for real 5-tuple rules and OpenFlow rules, respectively.

References

[1]

Wenwen Fu, Tao Li, and Zhigang Sun. 2018. FAS: Using FPGA to Accelerate and Secure SDN Software Switches. Security and Communication Networks, Vol. 2018 (2018), 5650205:1--5650205:13.

Digital Library

Google Scholar

[2]

Thilan Ganegedara, Weirong Jiang, and Viktor K. Prasanna. 2014. A Scalable and Modular Architecture for High-Performance Packet Classification. IEEE Trans. Parallel Distrib. Syst., Vol. 25, 5 (2014), 1135--1144.

Digital Library

Google Scholar

[3]

Weirong Jiang and Viktor K. Prasanna. 2009. Field-split parallel architecture for high performance multi-match packet classification using FPGAs. In SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, Calgary, Alberta, Canada, August 11--13, 2009, Friedhelm Meyer auf der Heide and Michael A. Bender (Eds.). ACM, 188--196.

Google Scholar

[4]

Bojie Li, Kun Tan, Layong Larry Luo, Yanqing Peng, Renqian Luo, Ningyi Xu, Yongqiang Xiong, and Peng Cheng. 2016. ClickNP: Highly flexible and High-performance Network Processing with Reconfigurable Hardware. In Proceedings of the ACM SIGCOMM 2016 Conference, Florianopolis, Brazil, August 22--26, 2016, Marinho P. Barcellos, Jon Crowcroft, Amin Vahdat, and Sachin Katti (Eds.). ACM, 1--14.

Digital Library

Google Scholar

[5]

Jivr 'i Matouvs ek, Gianni Antichi, Adam Lucansky, Andrew W. Moore, and Jan Korenek. 2017. ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution. In ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2017, Beijing, China, May 18--19, 2017. IEEE, 204--216.

Digital Library

Google Scholar

[6]

Yun Rock Qu and Viktor K. Prasanna. 2016. High-Performance and Dynamically Updatable Packet Classification Engine on FPGA . IEEE Trans. Parallel Distrib. Syst., Vol. 27, 1 (2016), 197--209.

Digital Library

Google Scholar

[7]

David E. Taylor. 2005. Survey and taxonomy of packet classification techniques. ACM Comput. Surv., Vol. 37, 3 (2005), 238--275.

Digital Library

Google Scholar

[8]

David E. Taylor and Jonathan S. Turner. 2007. ClassBench: a packet classification benchmark. IEEE/ACM Trans. Netw., Vol. 15, 3 (2007), 499--511.

Digital Library

Google Scholar

[9]

Tao Zhao, Tao Li, Biao Han, Zhigang Sun, and Jinfeng Huang. 2016. Design and implementation of Software Defined Hardware Counters for SDN . Computer Networks, Vol. 102 (2016), 129--144.

Digital Library

Google Scholar

Cited By

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Li CLi TLi JShi ZWang B(2020)Enabling Packet Classification with Low Update Latency for SDN Switch on FPGASustainability10.3390/su1208306812:8(3068)Online publication date: 11-Apr-2020
https://doi.org/10.3390/su12083068
Fahad MKhan BBilal RYoung RBeard CZaidi S(2020)Multibillion packet lookup for next generation networksComputers & Electrical Engineering10.1016/j.compeleceng.2020.10661284(106612)Online publication date: Jun-2020
https://doi.org/10.1016/j.compeleceng.2020.106612

Index Terms

A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement)
1. Networks
  1. Network algorithms
    1. Data path algorithms
      1. Packet classification

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Published In

SPAA '19: The 31st ACM Symposium on Parallelism in Algorithms and Architectures

June 2019

410 pages

ISBN:9781450361842

DOI:10.1145/3323165

General Chair:
Christian Scheideler
Paderborn University, Germany
,
Program Chair:
Petra Berenbrink
University of Hamburg, Germany

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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EATCS: European Association for Theoretical Computer Science

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Published: 17 June 2019

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National Natural Science Foundation of China
Research Project of National University of Defense Technology

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SPAA '19: 31st ACM Symposium on Parallelism in Algorithms and Architectures

June 22 - 24, 2019

AZ, Phoenix, USA

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SPAA '19 Paper Acceptance Rate 34 of 109 submissions, 31%;

Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Li CLi TLi JShi ZWang B(2020)Enabling Packet Classification with Low Update Latency for SDN Switch on FPGASustainability10.3390/su1208306812:8(3068)Online publication date: 11-Apr-2020
https://doi.org/10.3390/su12083068
Fahad MKhan BBilal RYoung RBeard CZaidi S(2020)Multibillion packet lookup for next generation networksComputers & Electrical Engineering10.1016/j.compeleceng.2020.10661284(106612)Online publication date: Jun-2020
https://doi.org/10.1016/j.compeleceng.2020.106612

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High throughput architecture for packet classification using FPGA

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules

Large-scale wire-speed packet classification on FPGAs

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High throughput architecture for packet classification using FPGA

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules

Large-scale wire-speed packet classification on FPGAs

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