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Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

Authors:

Lei He,

Kevin M. LepakAuthors Info & Claims

ISPD '00: Proceedings of the 2000 international symposium on Physical design

Pages 55 - 60

https://doi.org/10.1145/332357.332374

Published: 01 May 2000 Publication History

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Cited By

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Jordan JEsteve VDede ESanchis EMaset EFerreres AEjea JCases C(2016)Test bench for coupling and shielding magnetic field2016 ESA Workshop on Aerospace EMC (Aerospace EMC)10.1109/AeroEMC.2016.7504542(1-5)Online publication date: May-2016
https://doi.org/10.1109/AeroEMC.2016.7504542
Nagendra Babu GKaushik BBulusu AMajumder M(2012)Low complexity encoder for crosstalk reduction in RLC modeled interconnectsProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_5(40-45)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_5
Nagendra Babu GKaushik BBulusu A(2012)Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI InterconnectsAdvances in Computer Science, Engineering & Applications10.1007/978-3-642-30157-5_73(735-744)Online publication date: 2012
https://doi.org/10.1007/978-3-642-30157-5_73
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Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

In this article, we first show that existing net ordering formulations to minimize noise are no longer sufficient with the presence of inductive noise, and shield insertion is needed to minimize inductive noise. Using a K_eff model as the figure of merit ...
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ICCAD '00: Proceedings of the 2000 international conference on Computer-aided design

In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion ...
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Published In

ISPD '00: Proceedings of the 2000 international symposium on Physical design

May 2000

215 pages

ISBN:1581131917

DOI:10.1145/332357

Chairmen:
Manfred Wiesel,
Dwight Hill
Synopsys, Mountain View, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 2000

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Jordan JEsteve VDede ESanchis EMaset EFerreres AEjea JCases C(2016)Test bench for coupling and shielding magnetic field2016 ESA Workshop on Aerospace EMC (Aerospace EMC)10.1109/AeroEMC.2016.7504542(1-5)Online publication date: May-2016
https://doi.org/10.1109/AeroEMC.2016.7504542
Nagendra Babu GKaushik BBulusu AMajumder M(2012)Low complexity encoder for crosstalk reduction in RLC modeled interconnectsProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_5(40-45)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_5
Nagendra Babu GKaushik BBulusu A(2012)Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI InterconnectsAdvances in Computer Science, Engineering & Applications10.1007/978-3-642-30157-5_73(735-744)Online publication date: 2012
https://doi.org/10.1007/978-3-642-30157-5_73
Nagendra Babu GAgarwal DKaushik BManhas SKumar B(2011)Crosstalk avoidance in RLC modeled interconnects using low power encoder2011 IEEE Recent Advances in Intelligent Computational Systems10.1109/RAICS.2011.6069443(921-924)Online publication date: Sep-2011
https://doi.org/10.1109/RAICS.2011.6069443
Nagendra Babu GAgarwal DKaushik BManhas S(2011)Power and Crosstalk Reduction Using Bus Encoding Technique for RLC Modeled VLSI InterconnectTrends in Network and Communications10.1007/978-3-642-22543-7_43(424-434)Online publication date: 2011
https://doi.org/10.1007/978-3-642-22543-7_43
HUNG PLOU YLI Y(2009)Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting RoutingIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.880E92-A:3(880-889)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.880
Dao VEtoh TTanaka MAkino T(2009)Novel layout technique for on‐chip inductance minimizationMicroelectronics International10.1108/1356536091098150826:3(3-8)Online publication date: 31-Jul-2009
https://doi.org/10.1108/13565360910981508
Hung PLou YLi Y(2008)Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479788(514-519)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479788
Pasricha SDutt N(2008)Encoding Techniques for On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00007-4(253-300)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00007-4
Liu YHwang T(2007)Crosstalk-Aware Domino-Logic SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88574026:6(1155-1161)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.885740
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