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Cost based tradeoff analysis of standard cell designs

Authors:

Peng Li,

Pranab K. Nag,

Wojciech MalyAuthors Info & Claims

SLIP '00: Proceedings of the 2000 international workshop on System-level interconnect prediction

Pages 129 - 135

https://doi.org/10.1145/333032.333043

Published: 08 April 2000 Publication History

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References

[1]

Kai-Win Lee and Carl Sechen, "A New Global Router for Row-based Layout," Digest of Technical Papers, ICCAD-88, 180-183 (Nov. 1988).

Google Scholar

[2]

Patrick Hung and Michael J. Flynn, "Stochastic Congestion Model for VLSI Systems," Technical Report No. CSL-TR-97- 737, Stanford University (Oct. 1997).

Digital Library

Google Scholar

[3]

J. T. Mowchenko, "A Lower Bound on Channel Density After Global Routing," IEEE Trans. Computer-aided Design, vol. 8, 574-577 (May 1989).

Digital Library

Google Scholar

[4]

B.T. Murphy, "Cost size optima of monolithic integrated circuits," Proceedings of the IEEE, vol. 52, 1537-1545 (1964).

Crossref

Google Scholar

[5]

R. Seeds, "Yield and cost analysis of bipolar LSI," IEEE Int. Electron Devices Meeting (1967).

Google Scholar

[6]

R.M. Warner, Jr., "Applying a composite model to the IC yield problem," IEEE J. Solid-State Circuits, vol. SC-9, 86- 95 (June 1974).

Crossref

Google Scholar

[7]

C.H. Stapper, "On a composite model to the IC yield problem," IEEE Journal of Solid-State Circuits, vol. SC-10, 537-539 (1975).

Crossref

Google Scholar

[8]

C.H. Stapper, A.N. McLaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partial good product," IBM Journal of Research and Development, vol. 24, 398-409 (1980).

Digital Library

Google Scholar

[9]

C.H. Stapper and R.J. Rosner, "A simple method for modeling VLSI yields," Solid State Electronics, vol. 25, 487- 489 (1982).

Crossref

Google Scholar

[10]

W. Maly and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation," Electronics Letters, 17th Vol. 19, No. 6, 226-227 (March 1983).

Crossref

Google Scholar

[11]

A.V. Ferris-Prabhu, Modeling the critical area in yield forecasts," IEEE Journal of Solid State Circuits, vol. SC-20, no. 4, 874-878 (Aug. 1985).

Crossref

Google Scholar

[12]

A. V. Ferris-Prabhu, "Defect size variations and their effect on the critical area of VLSI devices," IEEE Journal Solid-State Circuits, vol. SC-20, 878-880 (Aug. 1985).

Crossref

Google Scholar

[13]

W. Maly, "Modeling of lithography-related yield losses for CAD of VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. CAD-4, 161-177 (July 1985).

Google Scholar

[14]

D.M.H. Walker, "Yield Simulation for Integrated Circuits," Boston: Kluwer Academic Publishers (1987).

Google Scholar

[15]

Pranab K. Nag and Wojciech Maly, "Yield Estimation of VLSI circuits," Techcon'90, 267-270 (Oct. 1990).

Google Scholar

[16]

T.L. Michalka, R.C. Varshney, and J.D. Meindl, "A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy," IEEE Transactions of Semiconductor Manufacturing, vol. 3, no. 3, 116-127 (Aug. 1990) .

Crossref

Google Scholar

[17]

18. J. Pineda de Gyvez and C. Di, "IC defect sensitivity for footprint-type spot defects," IEEE Transactions on Computer-Aided Design, vol. 11, no. 5, 638-658 (May 1992).

Digital Library

Google Scholar

[18]

J. Khare, D.B.I. Feltham and W. Maly, "Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits," IEEE Journal of Solid-State Circuits, vol. 28, no. 2, 146-156 (Feb. 1993).

Crossref

Google Scholar

[19]

Pranab K. Nag and Wojciech Maly, "Hierarchical Extraction of Critical Area for Shorts in Very Large ICs," Proceedings of The IEEE Inter. Workshop on Defect And Fault Tolerance in VLSI Systems, 19-27 (Nov. 1995).

Digital Library

Google Scholar

[20]

Hans T. Heineken and Wojciech Maly, "Interconnect Yield Model for Manufacturability Prediction in Synthesis of Standard Cell Based Designs," Digest of Technical Papers, ICCAD-96, 368-373 (Nov 1996).

Digital Library

Google Scholar

[21]

W. Maly, H. Heineken, J. Khare and P. K. Nag, "Design for Manufacturability in Submicron Domain," in Proc. of Int. Conf. on Computer-Aided Design, San Jose, Ca., 690-697 (Nov. 1996).

Digital Library

Google Scholar

[22]

Pranab K. Nag and Wojciech Maly, "Excel Based Cost Model," Technical Report No. CMUCAD-00-10, Carnegie Mellon University (July 1999).

Google Scholar

[23]

Philip Chong and Robert K. Brayton, "Estimating and Optimizing Routing Utilization in DSM Design," Workshop on System-Level Interconnect Prediction, SLIP' 99, 97-102 (April 1999).

Google Scholar

[24]

David N. Deutsch, "A "Dogleg" Channel Router," Proceeding. of 13th ACM/IEEE Design Automation Conf., 425-430 (1976).

Digital Library

Google Scholar

[25]

N. Hasan, G. Vijayan and C. K. Wong, "A Neighborhood Improvement Algorithm for Rectilinear Steiner Trees," Int. Symposium on Circuits and Systems, 2869-2872 (1990).

Google Scholar

[26]

Naveed Sherwani, "Algorithms for VLSI Physical Design Automation," Kluwer Academic Publishers, Second Edition (1995).

Digital Library

Google Scholar

[27]

Jeremy Zelsnack, "Modeling-Based Optimization of Number of Metal Layers," MS Thesis, Carnegie Mellon University, Report CMUCAD 98-17 (May 1998).

Google Scholar

[28]

W. R. Heller, C. G. His, W. F. Mikhail, W. E. Donath, "Prediction of Wire Space Requirements of LSI," Design Automation Conf., 32-42 (1997).

Digital Library

Google Scholar

[29]

A. A. El-Gamal, "Two-dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits," IEEE Trans. On Circuits and Systems, vol. CAS-28, 127-138 (Feb. 1981).

Google Scholar

[30]

S. Sastry, A. C. Parker, "Stochastic Models for Wireability Analysis of Gate Arrays," IEEE Trans. On Computer-aided Design, vol. CAD-5, 53-65 (Jan.1986).

Google Scholar

[31]

Kusnadi and J. Carothers, "A Method of Measuring Nets Routability for MCM's General Area Routing Problems," ISPD'99, 186-192 (1999).

Digital Library

Google Scholar

[32]

Jeffery A. Davis, Vivek K. De, and James D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)-Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation", IEEE Trans. On Electron Devices, vol. 45, no. 3 (March 1998).

Crossref

Google Scholar

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Aitken R(2006)The Design and Validation of IP for DFM/DFY Assurance2006 IEEE International Test Conference10.1109/TEST.2006.297742(1-7)Online publication date: Oct-2006
https://doi.org/10.1109/TEST.2006.297742
Aitken R(2006)DFM Metrics for Standard CellsProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.50(491-496)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.50
Wadekar SParker A(2004)Interconnect-based system-level energy and power prediction to guide architecture explorationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82583212:4(373-380)Online publication date: 1-Apr-2004
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SLIP '00: Proceedings of the 2000 international workshop on System-level interconnect prediction

April 2000

149 pages

ISBN:1581132492

DOI:10.1145/333032

Chairmen:
Dirk Stroobandt
Ghent Univ., Gent, Belgium
,
Phillip Christie
Univ. of Delaware
,
Andrew Kahng
Univ. of California-Los Angles, Los Angeles

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 April 2000

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SLIP00: International Workshop on System-Level Interconnect Prediction

April 8 - 9, 2000

California, San Diego, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Aitken R(2006)The Design and Validation of IP for DFM/DFY Assurance2006 IEEE International Test Conference10.1109/TEST.2006.297742(1-7)Online publication date: Oct-2006
https://doi.org/10.1109/TEST.2006.297742
Aitken R(2006)DFM Metrics for Standard CellsProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.50(491-496)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.50
Wadekar SParker A(2004)Interconnect-based system-level energy and power prediction to guide architecture explorationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82583212:4(373-380)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.825832
Christie PPineda de Gyvez JChristie PDavis JSylvester D(2001)Pre-layout prediction of interconnect manufacturabilityProceedings of the 2001 international workshop on System-level interconnect prediction10.1145/368640.368826(167-173)Online publication date: 1-Mar-2001
https://dl.acm.org/doi/10.1145/368640.368826

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