research-article

FPGA hardware linear regression implementation using fixed-point arithmetic

Authors:

Willian de Assis Pedrobon Ferreira,

Alexandre César Rodrigues da SilvaAuthors Info & Claims

SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design

Article No.: 10, Pages 1 - 6

https://doi.org/10.1145/3338852.3339853

Published: 26 August 2019 Publication History

Abstract

In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW.

References

[1]

Juan José Rodríguez Andina, Eduardo De la Torre Arnanz, and Maria Dolores Valdes. 2017. FPGAs: Fundamentals, Advanced Features, and Applications in Industrial Electronics. CRC Press.

[2]

D. Chen and S. Ko. 2007. Design and Implementation of Decimal Reciprocal Unit. In 2007 Canadian Conference on Electrical and Computer Engineering. 1094--1097.

[3]

Lattice Semiconductor Corporation. 2009. DSP Guide for FPGAs.

[4]

Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, and Mark Salmon. 2018. CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems. 2018 28th International Conference on Field Programmable Logic and Applications (FPL) (2018), 389--3894.

[5]

J. Dean, D. Patterson, and C. Young. 2018. A New Golden Age in Computer Architecture: Empowering the Machine-Learning Revolution. IEEE Micro 38, 2 (Mar 2018), 21--29.

[6]

Pablo Royer del Barrio, Miguel Ángel Sánchez Marcos, Marisa López Vallejo, and Carlos Alberto López Barrio. 2011. Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs. In Proceedings of 26th Conference on Design of Circuits and Integrated Systems. http://oa.upm.es/12192/

[7]

Intel FPGA. 2019. DSP Builder dor Intel FPGAS. Retrieved May 31, 2019 from https://www.intel.la/content/www/xl/es/software/programmable/quartus-prime/dsp-builder.html

[8]

A. Habegger, A. Stahel, J. Goette, and M. Jacomet. 2010. An Efficient Hardware Implementation for a Reciprocal Unit. In 2010 Fifth IEEE International Symposium on Electronic Design, Test Applications. 183--187.

Digital Library

[9]

K. Kara, D. Alistarh, G. Alonso, O. Mutlu, and C. Zhang. 2017. FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 160--167.

[10]

F. Liang, Y. Yang, G. Zhang, X. Zhang, and B. Wu. 2018. Design of 16-bit fixed-point CNN coprocessor based on FPGA. In 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP). 1--5.

[11]

L. Ma, L. Lavagno, M. T. Lazarescu, and A. Arif. 2017. Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis. IEEE Access 5 (2017), 18953--18974.

[12]

M. Mohammadi, A. Al-Fuqaha, S. Sorour, and M. Guizani. 2018. Deep Learning for IoT Big Data and Streaming Analytics: A Survey. IEEE Communications Surveys Tutorials (2018), 1--1.

[13]

R. Fernandez Molanes, K. Amarasinghe, J. Rodriguez-Andina, and M. Manic. 2018. Deep Learning and Reconfigurable Platforms in the Internet of Things: Challenges and Opportunities in Algorithms and Hardware. IEEE Industrial Electronics Magazine 12, 2 (June 2018), 36--49.

[14]

D. H. Noronha, P. H. W. Leong, and S. J. E. Wilton. 2018. Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks. In 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). 178--185.

[15]

Josh Patterson and Adam Gibson. 2017. Deep learning: A practitioner's approach. "O'Reilly Media, Inc.".

[16]

J. C. Porcello. 2017. Designing and implementing Machine Learning Algorithms for advanced communications using FPGAs. In 2017 IEEE Aerospace Conference. 1--10.

[17]

George AF Seber and Alan J Lee. 2012. Linear regression analysis. Vol. 329. John Wiley & Sons.

[18]

Hendrik Woehrle and Frank Kirchner.2018. CAEMO - A Flexible and scalable high performance matrix algebra coprocessor for embedded reconfigurable computing systems. Microprocessors and Microsystems 56 (2018), 47 -- 63.

Digital Library

[19]

Xilinx. 2019. DSP Solutions. Retrieved May 31, 2019 from https://www.xilinx.com/products/technology/dsp.html

[20]

Qingchen Zhang, Laurence T. Yang, Zhikui Chen, and Peng Li. 2018. A survey on deep learning for big data. Information Fusion 42 (2018), 146 -- 157.

Cited By

Guo CLuk WWarren ALevine JBrookes P(2023)Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP57973.2023.00028(102-109)Online publication date: Jul-2023
https://doi.org/10.1109/ASAP57973.2023.00028
Sengupta AChaurasia RRathor M(2023)HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learningThe Journal of Engineering10.1049/tje2.122992023:8Online publication date: 14-Aug-2023
https://doi.org/10.1049/tje2.12299
R NV RRao M(2022)Accelerated Piece-Wise-Linear Implementation Of Floating-Point Power Function2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9970828(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9970828
Show More Cited By

Index Terms

FPGA hardware linear regression implementation using fixed-point arithmetic
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
      1. Digital signal processing
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs

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cover image ACM Conferences

SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design

August 2019

204 pages

ISBN:9781450368445

DOI:10.1145/3338852

General Chair:
João Martino
USP, Brazil
,
Program Chairs:
Marcelo Lubaszewski
UFRGS, Brazil
,
Matteo Reorda
Politec. di Torino, Italy

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE Circuits & Systems Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 August 2019

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

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SBCCI '19

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SIGDA

SBCCI '19: 32nd Symposium on Integrated Circuits and Systems Design

August 26 - 30, 2019

São Paulo, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Guo CLuk WWarren ALevine JBrookes P(2023)Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP57973.2023.00028(102-109)Online publication date: Jul-2023
https://doi.org/10.1109/ASAP57973.2023.00028
Sengupta AChaurasia RRathor M(2023)HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learningThe Journal of Engineering10.1049/tje2.122992023:8Online publication date: 14-Aug-2023
https://doi.org/10.1049/tje2.12299
R NV RRao M(2022)Accelerated Piece-Wise-Linear Implementation Of Floating-Point Power Function2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9970828(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9970828
Xu SWang FWang HRomberg J(2020)In-Field Performance Optimization for mm-Wave Mixed-Signal Doherty Power Amplifiers: A Bandit ApproachIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.3022936(1-14)Online publication date: 2020
https://doi.org/10.1109/TCSI.2020.3022936
Costa Vde Araujo Gewehr CVicenzi JCarara Ede Oliveira L(2020)Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI50935.2020.9189923(1-6)Online publication date: Aug-2020
https://doi.org/10.1109/SBCCI50935.2020.9189923
Asuncion SLopez-Vallejo MGrajal J(2020)Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS51330.2020.9268633(1-6)Online publication date: 18-Nov-2020
https://doi.org/10.1109/DCIS51330.2020.9268633

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