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- Gonzalez MBol D(2023)Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137143(1-6)Online publication date: Apr-2023
- Krishnan NVasundhara Patel KJadhav M(2019)Comparative Study of gm/ID Methodology for Low-Power ApplicationsEmerging Research in Electronics, Computer Science and Technology10.1007/978-981-13-5802-9_83(949-959)Online publication date: 24-Apr-2019
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