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Convex delay models for transistor sizing

Authors:

Mahesh Ketkar,

Kishore Kasamsetty,

Sachin SapatnekarAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 655 - 660

https://doi.org/10.1145/337292.337607

Published: 01 June 2000 Publication History

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Abstract

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.

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Jiang SSong YZeng WZhang HCai SLu X(2023)New results on adaptive fixed-time control for convex-delayed neural networksISA Transactions10.1016/j.isatra.2022.08.027134(134-143)Online publication date: Mar-2023
https://doi.org/10.1016/j.isatra.2022.08.027
Stefanidis AMangiras DNicopoulos CChinnery DDimitrakopoulos G(2021)Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302554140:8(1672-1686)Online publication date: Aug-2021
https://doi.org/10.1109/TCAD.2020.3025541
Janet M. Roveda J(2014)Robust Optimization for Gate Sizing Considering Non-Gaussian Local VariationsApplied Mathematics10.4236/am.2014.51624505:16(2558-2569)Online publication date: 2014
https://doi.org/10.4236/am.2014.516245
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Convex delay models for transistor sizing

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DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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Jiang SSong YZeng WZhang HCai SLu X(2023)New results on adaptive fixed-time control for convex-delayed neural networksISA Transactions10.1016/j.isatra.2022.08.027134(134-143)Online publication date: Mar-2023
https://doi.org/10.1016/j.isatra.2022.08.027
Stefanidis AMangiras DNicopoulos CChinnery DDimitrakopoulos G(2021)Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302554140:8(1672-1686)Online publication date: Aug-2021
https://doi.org/10.1109/TCAD.2020.3025541
Janet M. Roveda J(2014)Robust Optimization for Gate Sizing Considering Non-Gaussian Local VariationsApplied Mathematics10.4236/am.2014.51624505:16(2558-2569)Online publication date: 2014
https://doi.org/10.4236/am.2014.516245
Shi BZhang YSrivastava A(2012)Accelerating Gate Sizing Using Graphics Processing UnitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216453931:1(160-164)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2164539
Liao CHu S(2011)Approximation scheme for restricted discrete gate sizing targeting delay minimizationJournal of Combinatorial Optimization10.1007/s10878-009-9267-021:4(497-510)Online publication date: 1-May-2011
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Ghosh SRoy K(2010)Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale EraProceedings of the IEEE10.1109/JPROC.2010.205723098:10(1718-1751)Online publication date: Oct-2010
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Sun JWang J(2010)Robust gate sizing by Uncertainty Second Order Cone2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450434(291-298)Online publication date: Mar-2010
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Ghosh S(2010)Effect of Variations and Variation Tolerance in Logic CircuitsLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_3(83-108)Online publication date: 25-Oct-2010
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Huebbers FDasdan AIsmail YGielen G(2007)Multi-layer interconnect performance corners for variation-aware timing analysisProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326223(713-718)Online publication date: 5-Nov-2007
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Coarse-grain MTCMOS sleep transistor sizing using delay budgeting

Crosstalk noise optimization by post-layout transistor sizing

Effective analytical delay model for transistor sizing

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Coarse-grain MTCMOS sleep transistor sizing using delay budgeting

Crosstalk noise optimization by post-layout transistor sizing

Effective analytical delay model for transistor sizing

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