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SIP: Boosting Up Graph Computing by Separating the Irregular Property Data

Published: 07 September 2020 Publication History

Abstract

Graph analytics is an important class of applications and is one of the cornerstone of big-data workloads. Unfortunately, due to poor data locality in most graph applications, conventional general-purpose computer architectures are unable to perform the best of their processing abilities. The main source of poor locality comes from accessing vertex properties. Upper-level caches cannot hold data blocks long enough due to their limited capacity and the long reuse distance of vertex properties. Moreover, accesses to properties can evict other useful data with good locality, which causes more conflicting misses. In this work, a small cache is added exclusively for the properties to solve this problem. We further enhance this structure with prefetchers to increase the hit rate of properties and improve performance of system. Experimental results show that compared to two state-of-the-art prefetcher and accelerator for graph computing, our proposed architecture achieves 1.13x-2.54x and 1.04x-1.27x performance improvements. In the meanwhile, the energy consumptions can be saved by 6.41%-13.43% and 34.67%-43.92% respectively.

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Cited By

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  • (2024)PDG: A Prefetcher for Dynamic Graph UpdatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333588043:4(1246-1259)Online publication date: Apr-2024
  • (2022)DBR: A Depth-Branch-Resorting Algorithm for Locality Exploration in Graph Processing2022 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC)10.23919/APSIPAASC55919.2022.9980127(178-184)Online publication date: 7-Nov-2022

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  1. SIP: Boosting Up Graph Computing by Separating the Irregular Property Data

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    cover image ACM Other conferences
    GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
    September 2020
    597 pages
    ISBN:9781450379441
    DOI:10.1145/3386263
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 07 September 2020

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    Author Tags

    1. cache hierarchy
    2. domain-specific architecture
    3. graph computing

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    Funding Sources

    • Beijing Natural Science Foundation
    • National Science Foundation

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    GLSVLSI '20
    GLSVLSI '20: Great Lakes Symposium on VLSI 2020
    September 7 - 9, 2020
    Virtual Event, China

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    View all
    • (2024)PDG: A Prefetcher for Dynamic Graph UpdatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333588043:4(1246-1259)Online publication date: Apr-2024
    • (2022)DBR: A Depth-Branch-Resorting Algorithm for Locality Exploration in Graph Processing2022 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC)10.23919/APSIPAASC55919.2022.9980127(178-184)Online publication date: 7-Nov-2022

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