research-article

Model-based Design of Hardware SC Polar Decoders for FPGAs

Authors:

Bertrand Le Gal,

Jerémie Crenne,

Christophe JegoAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 13, Issue 2

Article No.: 10, Pages 1 - 27

https://doi.org/10.1145/3391431

Published: 30 May 2020 Publication History

Abstract

Polar codes are a new error correction code family that should be benchmarked and evaluated in comparison to LDPC and turbo-codes. Indeed, recent advances in the 5G digital communication standard recommended the use of polar codes in EMBB control channels. However, in many cases, the implementation of efficient FEC hardware decoders is challenging. Specialised knowledge is required to enable and facilitate testing, rapid design iterations, and fast prototyping. In this article, a model-based design methodology to generate efficient hardware SC polar code decoders is presented. With HLS design process and tools, we demonstrate how FPGA system designers can quickly develop complex hardware systems with good performances. The favourable impact of design space exploration is underlined on achievable performances when a relevant computation model is used. The flexibility of the abstraction layers is evaluated. Hardware decoder generation efficiency is assessed and compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit length, pruning level, and working frequency help to design high-throughput decoders with moderate hardware complexities. Decoding throughputs higher than 300 Mbps are achieved on an Xilinx Virtex-7 device and on an Altera Stratix IV device.

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Cited By

Mouhoubi ONour CBaghdadi A(2022)On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes2022 11th International Symposium on Signal, Image, Video and Communications (ISIVC)10.1109/ISIVC54825.2022.9800721(1-6)Online publication date: 18-May-2022
https://doi.org/10.1109/ISIVC54825.2022.9800721
Almorin HLe Gal BCrenne JJego CKissel V(2022)High-throughput FFT architectures using HLS tools2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9970886(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9970886
Mouhoubi ONour CBaghdadi A(2022)Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar CodesIEEE Access10.1109/ACCESS.2022.321629210(113980-113994)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3216292
Show More Cited By

Index Terms

Model-based Design of Hardware SC Polar Decoders for FPGAs
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
    2. High-level and register-transfer level synthesis
      1. Datapath optimization
2. Mathematics of computing
  1. Information theory
    1. Coding theory

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 13, Issue 2

June 2020

185 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3383521

Editor:
Deming Chen
University of Illinois, Urbana-Champaign Urbana

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Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2020

Online AM: 07 May 2020

Accepted: 01 March 2020

Revised: 01 January 2020

Received: 01 August 2019

Published in TRETS Volume 13, Issue 2

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Cited By

Mouhoubi ONour CBaghdadi A(2022)On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes2022 11th International Symposium on Signal, Image, Video and Communications (ISIVC)10.1109/ISIVC54825.2022.9800721(1-6)Online publication date: 18-May-2022
https://doi.org/10.1109/ISIVC54825.2022.9800721
Almorin HLe Gal BCrenne JJego CKissel V(2022)High-throughput FFT architectures using HLS tools2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9970886(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9970886
Mouhoubi ONour CBaghdadi A(2022)Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar CodesIEEE Access10.1109/ACCESS.2022.321629210(113980-113994)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3216292
kumar DSelvakumari R(2022)Semi-parallel polar decoder architecture using shift-register-based partial-sum computation for 5G mobile communicationsMaterials Today: Proceedings10.1016/j.matpr.2022.04.17162(4985-4990)Online publication date: 2022
https://doi.org/10.1016/j.matpr.2022.04.171

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