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Precise and Efficient Analysis of Context-Sensitive Cache Conflict Sets

Published: 12 June 2020 Publication History
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  • Abstract

    Bounding the Worst-Case Execution Time (WCET) of real-time software requires precise knowledge about the reachable program and hardware states that might be observed at runtime. The analysis of precise cache states is particularly important and challenging. Due to the high cost of cache misses the analysis precision may have an important impact on the obtainable WCET bounds, while the large state space of the cache's history leads to high analysis complexity.
    This work explores the use of cache summaries in order to optimize the computation of precise cache states. These cache summaries allow us to pre-compute the impact of executing a portion of a program, typically a function, on the cache state. This allows us, for instance, to skip the analysis of entire functions (including nested function calls) when the cache states within these functions are not relevant for the classification of memory accesses into hits/misses. Furthermore, the summaries can be extended to efficiently compute fully context-sensitive cache states. The summaries then not only allow to derive typical cache hit/miss classifications, but also provide fully context-sensitive cache persistence information.

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    Cited By

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    • (2023)Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00029(237-250)Online publication date: 5-Dec-2023
    • (2022)Precise, efficient, and context-sensitive cache analysisReal-Time Systems10.1007/s11241-021-09372-558:1(36-84)Online publication date: 1-Mar-2022

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    cover image ACM Other conferences
    RTNS '20: Proceedings of the 28th International Conference on Real-Time Networks and Systems
    June 2020
    177 pages
    ISBN:9781450375931
    DOI:10.1145/3394810
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    • INRIA: INRIA Saclay Île-de-France

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 12 June 2020

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    Author Tags

    1. Cache Analysis
    2. Cache Summaries
    3. Conflict Sets
    4. LRU Cache Replacement
    5. Worst-Case Execution Time

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    • (2023)Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00029(237-250)Online publication date: 5-Dec-2023
    • (2022)Precise, efficient, and context-sensitive cache analysisReal-Time Systems10.1007/s11241-021-09372-558:1(36-84)Online publication date: 1-Mar-2022

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