research-article

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers

Authors:

Shinya Tanimura,

Akira Tsuchiya,

Toshiyuki Inoue,

Keiji KishineAuthors Info & Claims

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

Pages 15 - 16

https://doi.org/10.1145/3394885.3431646

Published: 29 January 2021 Publication History

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Abstract

This paper presents a supply noise reduction in transimpedance amplifier (TIA) for optical interconnection. TIAs integrated in parallel suffer from inter-channel interference via the supply and the ground lines. We employ an RC filter to reduce the supply noise. The filter is inserted to the first stage of TIA and does not need extra power. The proposed circuit was fabricated in an 180-nm CMOS. The measurement results verify 38% noise reduction at 5 Gbps operation.

References

[1]

A. Hiratsuka, A. Tsuchiya, K. Tanaka, H. Fukuyama, N. Miura, H. Nosaka, and H. Onodera. 2018. A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. In IEEE Asian Solid-State Circuits Conference. 69--72. https://doi.org/10.1109/ASSCC.2018.8579296

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[2]

Takashi Takemoto, Hiroki Yamashita, TOru Yazaki, Norio Chujo, Young Lee, and Yasunobu Matsuoka. 2014. A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. IEEE Journal of Solid-State Circuits 49, 10 (Oct 2014), 2259--2276.

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[3]

Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, and Keiji Kishine. 2019. Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. In IEEE International System-on-Chip Conference. 161--164.

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Index Terms

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers
1. Hardware
  1. Very large scale integration design
    1. Analog and mixed-signal circuits
      1. Wireline communication

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ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

January 2021

930 pages

ISBN:9781450379991

DOI:10.1145/3394885

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 January 2021

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ASPDAC '21

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SIGDA

ASPDAC '21: 26th Asia and South Pacific Design Automation Conference

January 18 - 21, 2021

Tokyo, Japan

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ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Design of low-noise transimpedance amplifiers with capacitive feedback

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

Analysis and design techniques for supply-noise mitigation in phase-locked loops

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Recommendations

Design of low-noise transimpedance amplifiers with capacitive feedback

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

Analysis and design techniques for supply-noise mitigation in phase-locked loops

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