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Clock rate versus IPC: the end of the road for conventional microarchitectures

Published: 01 May 2000 Publication History

Abstract

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance—estimating both clock rate and IPC —of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

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        cover image ACM Conferences
        ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture
        June 2000
        327 pages
        ISBN:1581132328
        DOI:10.1145/339647
        • cover image ACM SIGARCH Computer Architecture News
          ACM SIGARCH Computer Architecture News  Volume 28, Issue 2
          Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
          May 2000
          325 pages
          ISSN:0163-5964
          DOI:10.1145/342001
          Issue’s Table of Contents
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        Published: 01 May 2000

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