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Modeling techniques for logic locking

Authors:

Joseph Sweeney,

Marijn J. H. Heule,

Lawrence PileggiAuthors Info & Claims

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Article No.: 80, Pages 1 - 9

https://doi.org/10.1145/3400302.3415668

Published: 17 December 2020 Publication History

Abstract

Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.

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Cited By

McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Sweeney JGarg DPileggi L(2024)Quantifying the Efficacy of Logic Locking Methods2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00096(541-546)Online publication date: 6-Jan-2024
https://doi.org/10.1109/VLSID60093.2024.00096
Tehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi F(2024)Advances in Logic LockingHardware Security10.1007/978-3-031-58687-3_2(53-142)Online publication date: 3-Apr-2024
https://doi.org/10.1007/978-3-031-58687-3_2
Show More Cited By

Index Terms

Modeling techniques for logic locking
1. Security and privacy
  1. Security in hardware

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cover image ACM Conferences

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

November 2020

1396 pages

ISBN:9781450380263

DOI:10.1145/3400302

General Chair:
Yuan Xie
Univ. of California, Santa Barbara, CA

Copyright © 2020 Owner/Author.

This work is licensed under a Creative Commons Attribution International 4.0 License.

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Published: 17 December 2020

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ICCAD '20: IEEE/ACM International Conference on Computer-Aided Design

November 2 - 5, 2020

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Sweeney JGarg DPileggi L(2024)Quantifying the Efficacy of Logic Locking Methods2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00096(541-546)Online publication date: 6-Jan-2024
https://doi.org/10.1109/VLSID60093.2024.00096
Tehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi F(2024)Advances in Logic LockingHardware Security10.1007/978-3-031-58687-3_2(53-142)Online publication date: 3-Apr-2024
https://doi.org/10.1007/978-3-031-58687-3_2
Kamali HAzar KFarahmandi FTehranipoor M(2023)SheLL: Shrinking eFPGA Fabrics for Logic Locking2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137211(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137211
Mankali LPatnaik SLimaye NKnechtel JSinanoglu O(2023) VIGILANT : Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325930042:11(3571-3584)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3259300
Zhong YGuin U(2023)Complexity Analysis of the SAT Attack on Logic LockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.324093342:10(3143-3156)Online publication date: Oct-2023
https://doi.org/10.1109/TCAD.2023.3240933
Rahman MGuo RKamali HRahman FFarahmandi FTehranipoor M(2023)ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM ApproachIEEE Access10.1109/ACCESS.2023.324490211(19741-19761)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3244902
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Post-satisfiability Era: Countermeasures and ThreatsUnderstanding Logic Locking10.1007/978-3-031-37989-5_8(155-212)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_8
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Logic Locking in Future IC Supply Chain EnvironmentsUnderstanding Logic Locking10.1007/978-3-031-37989-5_12(309-333)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_12
Nguyen QDupuis SFlottes MRouzeyre B(2022)SKG-Lock+: A Provably Secure Logic Locking SchemeCreating Significant Output CorruptionElectronics10.3390/electronics1123390611:23(3906)Online publication date: 25-Nov-2022
https://doi.org/10.3390/electronics11233906
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