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RTL-to-GDS design tools for monolithic 3D ICs

Published: 17 December 2020 Publication History

Abstract

In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool flow is based on commercial 2D tools and smart ways to extend them to conduct M3D design and simulation. We provide a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization. We also conduct IR-drop and thermal analysis on M3D designs to improve the reliability. To enhance the testability of our M3D designs, we develop design-for-test (DFT) methodologies and integrate a low-overhead built-in self-test module into our design for testing inter-layer vias (ILVs) as well as logic circuitries in the individual tiers. Our benchmark design is RISC-V Rocketcore, which is an open source processor. Our experiments show 8.1% of power, 19.6% of wirelength and 55.7% of area savings with M3D designs at iso-performance compared to its 2D counterpart. In addition, our IR-drop and thermal analyses indicate acceptable power and thermal integrity in our M3D design.

References

[1]
K. Arabi, K. Samadi, and Y. Du. 3D VLSI: A Scalable Integration Beyond 2D. In Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD '15, page 1--7, New York, NY, USA, 2015. Association for Computing Machinery.
[2]
K. Asanović et al. The Rocket Chip Generator. Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, Apr 2016.
[3]
P. Batude et al. 3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2(4):714--722, Dec 2012.
[4]
K. Chang et al. Cascade2D: A Design-aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1--8, Nov 2016.
[5]
A. Chaudhuri et al. Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. In 2019 IEEE European Test Symposium (ETS), pages 1--6, 2019.
[6]
D. Erb et al. Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. In 2015 IEEE 33rd VLSI Test Symposium (VTS), pages 1--6, 2015.
[7]
C. M. Fiduccia and R. M. Mattheyses. A Linear-Time Heuristic for Improving Network Partitions. In 19th Design Automation Conference, pages 175--181, June 1982.
[8]
G. Hills et al. Modern Microprocessor Built from Complementary Carbon Nanotube Transistors. Nature, 572:595--602, August 2019.
[9]
A. Jutman. Shift Register based TPG for At-speed Interconnect BIST. In 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716), volume 2, pages 751--754 vol. 2, 2004.
[10]
A. Koneru, S. Kannan, and K. Chakrabarty. A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(10):1942-1955, 2019.
[11]
B. W. Ku, K. Chang, and S. K. Lim. Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs. In Proceedings of the 2018 International Symposium on Physical Design, ISPD '18, page 90--97, New York, NY, USA, 2018. Association for Computing Machinery.
[12]
S. Panth et al. Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs. In 2014 IEEE/ACM International Symposium an Low Power Electronics and Design (ISLPED), pages 171--176, Aug 2014.
[13]
R. Pendurkar, A. Chatterjee, and Y. Zorian. Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1143--1158, 2001.
[14]
M. M. Shulaker et al. Monolithic 3D integration: A path from concept to reality. In 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1197--1202, 2015.
[15]
T. Srimani et al. Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node. In IEEE VLSI, 2020.
[16]
H. P. Wong et al. Carbon Nanotube Field Effect Transistors - Fabrication, Device physics, and Circuit Implications. In 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., pages 370--500 vol. 1, Feb 2003.

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  • (2023)Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137051(1-6)Online publication date: Apr-2023
  • (2023)A Multi-Objective Optimization Algorithm Based on Deep Learning for Circuit Partition2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218622(97-101)Online publication date: 8-May-2023
  • (2023)Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with Macros2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323747(1-6)Online publication date: 28-Oct-2023
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  1. RTL-to-GDS design tools for monolithic 3D ICs

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    cover image ACM Conferences
    ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design
    November 2020
    1396 pages
    ISBN:9781450380263
    DOI:10.1145/3400302
    • General Chair:
    • Yuan Xie
    This work is licensed under a Creative Commons Attribution International 4.0 License.

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    Published: 17 December 2020

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    Author Tags

    1. CNFET
    2. ILV dual-BIST
    3. design-for-test
    4. monolithic 3D IC
    5. physical design (EDA)

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    Overall Acceptance Rate 457 of 1,762 submissions, 26%

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    View all
    • (2023)Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137051(1-6)Online publication date: Apr-2023
    • (2023)A Multi-Objective Optimization Algorithm Based on Deep Learning for Circuit Partition2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218622(97-101)Online publication date: 8-May-2023
    • (2023)Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with Macros2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323747(1-6)Online publication date: 28-Oct-2023
    • (2022)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 21-Oct-2022

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