CCHL: Compression-Consolidation Hardware Logging for Efficient Failure-Atomic Persistent Memory Updates

Non-volatile memory (NVM) is emerging as a fast byte-addressable persistent memory (PM) that promises data persistence at the main memory level. One of the common choices for providing failure-atomic updates in PM is the write-ahead logging (WAL) technique. To mitigate logging overhead, recent studies propose WAL-based hardware logging designs that overlap log writes with transaction execution. However, existing hardware logging designs incur a large number of unnecessary log writes. Many log writes are still performed in the critical path, which causes high performance overhead, particularly for the multi-core systems with many threads.

In this paper, we propose a Compression-Consolidation Hardware Logging (CCHL) design that removes log writes from the critical path by eliminating unnecessary log writes and enabling delayed durable transaction commits. To reduce log writes, we design two log optimizations: intra-tx log compression and inter-tx log consolidation. The first optimization compresses log entries by logging only the data whose values are changed, while the second one consolidates log entries by combining multiple transactions. To enable delayed durability, CCHL exploits a small region of DRAM as a cache for log writes. Log entries are first buffered in the DRAM cache and then written back to PM by hardware, which allows transactions to commit without waiting for persisting log entries. Our evaluation shows that CCHL improves throughput by 47.4%, reduces PM write traffic by 36.1%, and reduces memory dynamic energy by 18.7% compared with the state-of-the-art design.