Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/3407197.3407619acmotherconferencesArticle/Chapter ViewAbstractPublication PagesiconsConference Proceedingsconference-collections
research-article

NCPower: Power Modelling for NVM-based Neuromorphic Chip

Published: 28 July 2020 Publication History

Abstract

Spiking neural networks (SNN) on non-volatile memory (NVM) based neuromorphic computing (NC) chips have been regarded as a promising solution in power constrained scenarios, such as Internet of Things (IoT), due to its low energy consumption. The high power efficiency of NC is due to various aspects including the non-von Neumann architecture of NC chip, low power NVM, and the event driven computation of SNN etc., and introduces a large space for low power design exploration. Therefore, a comprehensive quantitative study of the power modelling for such neuromorphic computing system is important for low power design. In this work, we propose NCPower, an energy consumption estimator for NVM-based neuromorphic chip. We systemically developed analytical models based on physical laws, and verify them by comparing the analytical results with measurement results from different neuromorphic chips. We integrated NCPower in a simulator, and analyzed the accuracy and energy consumption of both the traditional multi-spike based SNN and the new single-spike based SNN. It shows that the single-spike model has 7X energy efficiency over the multi-spike model, with similar accuracy under the CIFAR-10 dataset.

References

[1]
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, and Niraj K Jha. 2009. GARNET: A Detailed On-chip Network Model Inside a Full-system Simulator. In 2009 IEEE international symposium on performance analysis of systems and software. IEEE, 33–42.
[2]
Irem Boybat, Manuel Le Gallo, SR Nandakumar, Timoleon Moraitis, Thomas Parnell, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, and Evangelos Eleftheriou. 2018. Neuromorphic Computing with Multi-memristive Synapses. Nature communications 9, 1 (2018), 1–12.
[3]
Xiangyu Dong, Cong Xu, Yuan Xie, and Norman P Jouppi. 2012. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 7(2012), 994–1007.
[4]
SK Esser, PA Merolla, JV Arthur, AS Cassidy, R Appuswamy, A Andreopoulos, DJ Berg, JL McKinstry, T Melano, DR Barch, 2016. Convolutional Networks for Fast, Energy-Efficient Neuromorphic Computing. Preprint on ArXiv. http://arxiv. org/abs/1603.08270. Accessed 27 (2016).
[5]
Alessandro Grossi, Eduardo Perez, Cristian Zambelli, Piero Olivo, and Christian Wenger. 2016. Performance and Reliability Comparison of 1T-1R RRAM Arrays with Amorphous and Polycrystalline HfO2. In 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 80–83.
[6]
Daniele Ielmini and Stefano Ambrogio. 2019. Emerging Neuromorphic Devices. Nanotechnology 31, 9 (2019), 092001.
[7]
Sheng Li, Jung Ho Ahn, Richard D Strong, Jay B Brockman, Dean M Tullsen, and Norman P Jouppi. 2009. McPAT: an Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 469–480.
[8]
Tao Luo, Bingsheng He, Wei Zhang, and Douglas L Maskell. 2017. A novel Two-stage Modular Multiplier Based on Racetrack Memory for Asymmetric Cryptography. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 276–282.
[9]
Tao Luo, Wei Zhang, Bingsheng He, and Douglas Maskell. 2016. A Racetrack Memory Based In-memory Booth Multiplier for Cryptography Application. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 286–291.
[10]
Reza Salkhordeh, Onur Mutlu, and Hossein Asadi. 2019. An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. IEEE Trans. Comput. 68, 8 (2019), 1114–1130.
[11]
Catherine D Schuman, Thomas E Potok, Robert M Patton, J Douglas Birdwell, Mark E Dean, Garrett S Rose, and James S Plank. 2017. A Survey of Neuromorphic Computing and Neural Networks in Hardware. arXiv preprint arXiv:1705.06963(2017).
[12]
Evangelos Stromatias, Francesco Galluppi, Cameron Patterson, and Steve Furber. 2013. Power Analysis of Large-scale, Real-time Neural Networks on SpiNNaker. In The 2013 international joint conference on neural networks (IJCNN). IEEE, 1–8.
[13]
Jianshi Tang, Douglas Bishop, Seyoung Kim, Matt Copel, Tayfun Gokmen, Teodor Todorov, SangHoon Shin, Ko-Tao Lee, Paul Solomon, Kevin Chan, 2018. ECRAM as Scalable Synaptic Cell for High-speed, Low-power Neuromorphic Computing. In 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 13–1.
[14]
Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Huazhong Yang, Hai Li, and Yuan Xie. 2015. Energy Efficient RRAM Spiking Neural Network for Real Time Classification. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI. 189–194.
[15]
Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, and Ning Ge. 2016. A Holistic Tri-region MLC STT-RAM Design with Combined Performance, Energy, and Reliability Optimizations. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1285–1290.
[16]
Linda Wilson. 2013. International Technology Roadmap for Semiconductors (ITRS) Report. Semiconductor Industry Association 1 (2013).
[17]
Chris Yakopcic, Raqibul Hasan, Tarek M Taha, and Doug Palmer. 2015. SPICE Analysis of Dense Memristor Crossbars for Low Power Neuromorphic Processor Designs. In 2015 National Aerospace and Electronics Conference (NAECON). IEEE, 305–311.
[18]
Peng Yao, Huaqiang Wu, Bin Gao, Sukru Burc Eryilmaz, Xueyao Huang, Wenqiang Zhang, Qingtian Zhang, Ning Deng, Luping Shi, H-S Philip Wong, 2017. Face Classification Using Electronic Synapses. Nature communications 8, 1 (2017), 1–8.
[19]
Shimeng Yu, Bin Gao, Zheng Fang, Hongyu Yu, Jinfeng Kang, and H-S Philip Wong. 2013. A Low Energy Oxide-based Electronic Synaptic Device for Neuromorphic Visual Systems with Tolerance to Device Variation. Advanced Materials 25, 12 (2013), 1774–1779.
[20]
Dai Zhang, Ameya Bhide, and Atila Alvandpour. 2012. A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices. IEEE Journal of Solid-State Circuits 47, 7 (2012), 1585–1593.

Cited By

View all
  • (2024)Efficient Spiking Neural Networks With Radix EncodingIEEE Transactions on Neural Networks and Learning Systems10.1109/TNNLS.2022.319591835:3(3689-3701)Online publication date: Mar-2024
  • (2023)Simeuro: A Hybrid CPU-GPU Parallel Simulator for Neuromorphic Computing ChipsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.329179534:10(2767-2782)Online publication date: Oct-2023
  • (2022)Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing ElementsACM Transactions on Embedded Computing Systems10.1145/352406821:6(1-27)Online publication date: 12-Dec-2022

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
ICONS 2020: International Conference on Neuromorphic Systems 2020
July 2020
186 pages
ISBN:9781450388511
DOI:10.1145/3407197
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 July 2020

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. datasets
  2. gaze detection
  3. neural networks
  4. text tagging

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Funding Sources

  • Singapore Government?s Research, Innovation and Enterprise 2020 Plan (Advanced Manufacturing and Engineering domain)

Conference

ICONS 2020

Acceptance Rates

Overall Acceptance Rate 13 of 22 submissions, 59%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)15
  • Downloads (Last 6 weeks)2
Reflects downloads up to 02 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2024)Efficient Spiking Neural Networks With Radix EncodingIEEE Transactions on Neural Networks and Learning Systems10.1109/TNNLS.2022.319591835:3(3689-3701)Online publication date: Mar-2024
  • (2023)Simeuro: A Hybrid CPU-GPU Parallel Simulator for Neuromorphic Computing ChipsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.329179534:10(2767-2782)Online publication date: Oct-2023
  • (2022)Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing ElementsACM Transactions on Embedded Computing Systems10.1145/352406821:6(1-27)Online publication date: 12-Dec-2022

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

HTML Format

View this article in HTML Format.

HTML Format

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media