research-article

Enabling transparent hardware acceleration on Zynq SoC for scientific computing

Authors:

Luca Stornaiuolo,

Filippo Carloni,

Riccardo Pressiani,

Giuseppe Natale,

Marco Santambrogio, and

Donatella SciutoAuthors Info & Claims

ACM SIGBED Review, Volume 17, Issue 1

Pages 30 - 35

https://doi.org/10.1145/3412821.3412826

Published: 27 July 2020 Publication History

Abstract

In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into applications. In this work we build upon this framework to enable transparent hardware acceleration for scientific computations for Zynq. We do so by providing a custom NumPy library designed for PYNQ, as it is the de-facto scientific library for Python. We then demonstrate the effectiveness of the proposed approach on a biomedical use case involving the extraction of features from the Electroencephalography (EEG).

References

[1]

A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, et al., "A reconfigurable fabric for accelerating large-scale datacenter services," in Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, IEEE, 2014.

[2]

"IEEE Spectrum: The 2017 Top Programming Languages." https://spectrum.ieee.org/computing/software/the-2017-top-programming-languages (accessed: 5th of October 2017).

[3]

L. Stornaiuolo, M. Perini, M. D. Santambrogio, and D. Sciuto, "Fpga-based embedded system implementation of audio signal alignment," in 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 132--139, IEEE, 2019.

[4]

A. G. Schmidt, G. Weisz, and M. French, "Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs," in Proceedings of the 25th International Symposium on Field-Programmable Custom Computing Machines, FCCM '17, IEEE, 2017.

[5]

B. Janßen, P. Zimprich, and M. Hübner, "A dynamic partial reconfigurable overlay concept for PYNQ," in Field Programmable Logic and Applications (FPL), 2017 27th International Conference on, IEEE, 2017.

[6]

E. Koromilas, I. Stamelos, C. Kachris, and D. Soudris, "Spark acceleration on FPGAs: A use case on machine learning in Pynq," in Modern Circuits and Systems Technologies (MOCAST), 2017 6th International Conference on, IEEE, 2017.

[7]

T. Blum, M. R. Kristensen, and B. Vinter, "Transparent GPU execution of NumPy applications," in Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International, IEEE, 2014.

[8]

M. R. Kristensen, S. A. Lund, T. Blum, K. Skovhede, and B. Vinter, "Bohrium: unmodified NumPy code on CPU, GPU, and cluster," Python for High Performance and Scientific Computing (PyHPC '13), 2013.

[9]

D. Lockhart, G. Zibrat, and C. Batten, "PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research," in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-47, IEEE Computer Society, 2014.

[10]

P. Haglund, O. Mencer, W. Luk, and B. Tai, "PyHDL: Hardware Scripting with Python," in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2003.

[11]

E. Logaras, O. G. Hazapis, and E. S. Manolakos, "Python to Accelerate Embedded SoC Design: A Case Study for Systems Biology," ACM Trans. Embed. Comput. Syst., vol. 13, Mar. 2014.

Digital Library

[12]

V. J. Jiménez, L. Vilanova, I. Gelado, M. Gil, G. Fursin, and N. Navarro, "Predictive runtime code scheduling for heterogeneous architectures.," HiPEAC, vol. 9, 2009.

[13]

D. Bagni, A. Di Fresco, J. Noguera, and F. Vallina, "A zynq accelerator for floating point matrix multiplication designed with vivado hls," Application note, January, 2016.

[14]

I. Choi, I. Rhiu, Y. Lee, M. H. Yun, and C. S. Nam, "A systematic review of hybrid brain-computer interfaces: Taxonomy and usability perspectives," PloS one, vol. 12, no. 4, 2017.

[15]

A. Gramfort, M. Luessi, E. Larson, D. A. Engemann, D. Strohmeier, C. Brodbeck, L. Parkkonen, and M. S. Hämäläinen, "Mne software for processing meg and eeg data," NeuroImage, vol. 86, no. Supplement C, 2014.

[16]

E. Olejarczyk, L. Marzetti, V. Pizzella, and F. Zappasodi, "Comparison of connectivity analyses for resting state eeg data," Journal of Neural Engineering, vol. 14, no. 3, 2017.

[17]

G. Dornhege, B. Blankertz, G. Curio, and K. R. Muller, "Boosting bit rates in noninvasive eeg single-trial classifications by feature combination and multiclass paradigms," IEEE Transactions on Biomedical Engineering, vol. 51, June 2004.

Cited By

Agrawal KAsati A(2024)Improved Implementation of PYNQ-Based FFT Hardware Accelerator2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT)10.1109/DICCT61038.2024.10532842(414-418)Online publication date: 15-Mar-2024
https://doi.org/10.1109/DICCT61038.2024.10532842
De Laender GD'Hollander E(2023)ZyPy: Intercepting NumPy operations for acceleration on FPGAsProceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3597031.3597033(100-106)Online publication date: 14-Jun-2023
https://dl.acm.org/doi/10.1145/3597031.3597033

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Information & Contributors

Information

Published In

cover image ACM SIGBED Review

ACM SIGBED Review Volume 17, Issue 1

Special Issue on Embedded Operating Systems Workshop 2019 (EWiLi'19)

February 2020

58 pages

EISSN:1551-3688

DOI:10.1145/3412821

Editors:
Heechul Yun
University of Kansas
,
Sophie Quinton
INRIA Grenoble - Rhone-Alpes, France
,
Gedare Bloom
University of Colorado at Colorado Springs
,
Dionisio De Niz
Software Engineering Institute, Carnegie Mellon University

Issue’s Table of Contents

Copyright © 2020 Copyright is held by the owner/author(s).

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 July 2020

Published in SIGBED Volume 17, Issue 1

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Cited By

Agrawal KAsati A(2024)Improved Implementation of PYNQ-Based FFT Hardware Accelerator2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT)10.1109/DICCT61038.2024.10532842(414-418)Online publication date: 15-Mar-2024
https://doi.org/10.1109/DICCT61038.2024.10532842
De Laender GD'Hollander E(2023)ZyPy: Intercepting NumPy operations for acceleration on FPGAsProceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3597031.3597033(100-106)Online publication date: 14-Jun-2023
https://dl.acm.org/doi/10.1145/3597031.3597033

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