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Pipelined implementation of serial comparison based iterative sort on FPGA

Authors:

Jingyang Zhou,

Xiongkui Zhang,

Jiameng FanAuthors Info & Claims

AIAM2020: Proceedings of the 2nd International Conference on Artificial Intelligence and Advanced Manufacture

Pages 26 - 30

https://doi.org/10.1145/3421766.3421879

Published: 26 October 2020 Publication History

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Abstract

Sorting is a classic problem in computer science. Different kinds of sorting algorithms are required in different application scenarios. With regard to the real-time data processing applications implemented on FPGA, a faster throughput and more resource efficient sorting algorithm is needed to complete the data sorting. And the pipelined implementation of sorting algorithm is essential for improving the overall throughput. In this paper, a serial comparison based iterative sort algorithm is proposed and its implementation on FPGA is elaborated. To take advantages of the parallel characteristics of FPGA, the pipelined sorting module is realized by concatenating multiple serial comparison sorting submodules. Compared to other sorting algorithms implemented on FPGA, the serial comparison based iterative sort algorithm has the merit of requiring fewer resource consumptions, consuming less executing time and generating faster overall data throughput. The algorithm and its pipelined implementation have been successfully applied to the median filter of OS-CFAR processing in millimetre-wave MIMO radar, and their performance have been validated.

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Samahith SGovardhan SManogna RHitesh DSudeendra Kumar K(2023)Low Power Multidimensional Sorters using Clock Gating and Index Sorting2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)10.1109/CONECCT57959.2023.10234758(1-6)Online publication date: 14-Jul-2023
https://doi.org/10.1109/CONECCT57959.2023.10234758

Index Terms

Pipelined implementation of serial comparison based iterative sort on FPGA
1. Computing methodologies
  1. Concurrent computing methodologies
    1. Concurrent algorithms

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AIAM2020: Proceedings of the 2nd International Conference on Artificial Intelligence and Advanced Manufacture

October 2020

566 pages

ISBN:9781450375535

DOI:10.1145/3421766

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 26 October 2020

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AIAM2020: 2nd International Conference on Artificial Intelligence and Advanced Manufacture

October 15 - 17, 2020

Manchester, United Kingdom

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Samahith SGovardhan SManogna RHitesh DSudeendra Kumar K(2023)Low Power Multidimensional Sorters using Clock Gating and Index Sorting2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)10.1109/CONECCT57959.2023.10234758(1-6)Online publication date: 14-Jul-2023
https://doi.org/10.1109/CONECCT57959.2023.10234758

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A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

An FPGA implementation for neural networks with the FDFM processor core approach

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A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

An FPGA implementation for neural networks with the FDFM processor core approach

A novel AES-256 implementation on FPGA using co-processor based architecture

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