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Layout compaction for yield optimization via critical area minimization

Authors:

Youcef Bourai,

C.-J. Richard ShiAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 122 - 127

https://doi.org/10.1145/343647.343717

Published: 01 January 2000 Publication History

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References

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Cited By

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Dong XZhang L(2016)Advanced nanometer technology analog layout retargeting for lithography friendly design2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527477(1262-1265)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7527477
Andrus CGuthaus MBrunvard EStevens KCavallaro JZhang T(2012)Lithography-aware layout compactionProceedings of the great lakes symposium on VLSI10.1145/2206781.2206818(147-152)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206818
Lee YLin YLi Y(2011)Gridless wire ordering, sizing and spacing with critical area minimization2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770797(1-8)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770797
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Index Terms

Layout compaction for yield optimization via critical area minimization
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
2. Theory of computation
  1. Logic
  2. Models of computation

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

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Published: 01 January 2000

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DATE00: Design Automation and Test in Europe

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Dong XZhang L(2016)Advanced nanometer technology analog layout retargeting for lithography friendly design2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527477(1262-1265)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7527477
Andrus CGuthaus MBrunvard EStevens KCavallaro JZhang T(2012)Lithography-aware layout compactionProceedings of the great lakes symposium on VLSI10.1145/2206781.2206818(147-152)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206818
Lee YLin YLi Y(2011)Gridless wire ordering, sizing and spacing with critical area minimization2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770797(1-8)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770797
Pan DCho MKyung CChoi KHa S(2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356860(220-225)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356860
Pan DYu PCho MRamalingam AKim KRajaram AShi S(2008)Design for manufacturing meets advanced process control: A surveyJournal of Process Control10.1016/j.jprocont.2008.04.00718:10(975-984)Online publication date: Dec-2008
https://doi.org/10.1016/j.jprocont.2008.04.007
Iizuka TIkeda MAsada K(2007)Timing-aware cell layout de-compaction for yield optimization by critical area minimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1324053.132406315:6(716-720)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.5555/1324053.1324063
Cho MXiang HPuri RPan DLevitan S(2007)TROYProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278495(55-58)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278495
Yan JChiang B(2007)Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area MinimizationProceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems10.1109/VLSID.2007.158(899-906)Online publication date: 6-Jan-2007
https://dl.acm.org/doi/10.1109/VLSID.2007.158
Zhou QCai YLi DHong X(2007)A yield-driven gridless routerJournal of Computer Science and Technology10.1007/s11390-007-9092-922:5(653-660)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s11390-007-9092-9
Iizuka TIkeda MAsada KGielen G(2006)Timing-driven cell layout de-compaction for yield optimization by critical area minimizationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131731(884-889)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131731
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Nonlocal image denoising via adaptive tensor nuclear norm minimization

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