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System design based on single language and single-chip Java ASIP microcontroller

Authors:

Sérgio Akira Ito,

Luigi Carro,

Ricardo Pezzuol JacobiAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 703 - 709

https://doi.org/10.1145/343647.343899

Published: 01 January 2000 Publication History

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Otero JWagner FCarro L(2006)Reconfiguration of embedded java applicationsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899168(210-210)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1899168
L'Hours L(2005)Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)10.1109/ASAP.2005.37(127-133)Online publication date: 2005
https://doi.org/10.1109/ASAP.2005.37
Yanagisawa HUehara MMori H(2004)Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor DesignProceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 710.5555/977399.977951(831-837)Online publication date: 23-Mar-2004
https://dl.acm.org/doi/10.5555/977399.977951
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System design based on single language and single-chip Java ASIP microcontroller
1. Hardware

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 2000

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DATE00: Design Automation and Test in Europe

March 27 - 30, 2000

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Otero JWagner FCarro L(2006)Reconfiguration of embedded java applicationsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899168(210-210)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1899168
L'Hours L(2005)Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)10.1109/ASAP.2005.37(127-133)Online publication date: 2005
https://doi.org/10.1109/ASAP.2005.37
Yanagisawa HUehara MMori H(2004)Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor DesignProceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 710.5555/977399.977951(831-837)Online publication date: 23-Mar-2004
https://dl.acm.org/doi/10.5555/977399.977951
Amory ACota ÉLubaszewski MMoraes FNatividade da Silva Barros EWagner FCarro LRammig F(2004)Reducing test time with processor reuse in network-on-chip based systemsProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016602(111-116)Online publication date: 4-Sep-2004
https://dl.acm.org/doi/10.1145/1016568.1016602

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Dual-pipeline heterogeneous ASIP design

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Predicated Static Single Assignment

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Dual-pipeline heterogeneous ASIP design

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Predicated Static Single Assignment

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