Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA

In recent years, deep learning has flourished, and significant progress has been made in computer vision fields such as image classification, target detection, and image semantic segmentation. Target detection based on deep learning has also made remarkable achievements. However, most of the existing target detection methods are difficult to apply to mobile platforms with small size and low power consumption, and it is difficult to meet the requirements of real-time detection. The simple structure and fast speed of YOLO v2 opens up new ideas for real-time target detection. FPGA provides a lot of design resources, and uses the idea of parallel computing to accelerate the target detection algorithm, so that it can be applied on a small-scale, low-power embedded platform. The main purpose of this article is to realize the acceleration of YOLO v2 algorithm on FPGA platform by designing accelerator memory access module. Experiments have proved that compared with similar research results, this design can better balance speed and accuracy. The parallel read and write design of accelerator memory access module greatly improves the parallelism of the system and has better overall performance.