research-article

Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm

Authors:

Eros Camacho-Ruiz,

Santiago Sánchez-Solano,

Macarena C. Martínez-RodríguezAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 17, Issue 3

Article No.: 35, Pages 1 - 16

https://doi.org/10.1145/3445979

Published: 11 May 2021 Publication History

Abstract

Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.

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Cited By

He PBao TXie JAmin M(2023)FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum CryptographyACM Transactions on Reconfigurable Technology and Systems10.1145/356945716:3(1-23)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3569457
Khan SLee WKhalid AMajeed AHwang S(2023)Area-Optimized Constant-Time Hardware Implementation for Polynomial MultiplicationIEEE Embedded Systems Letters10.1109/LES.2022.318526515:1(5-8)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1109/LES.2022.3185265
He PBao TTu YXie J(2023)Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00021(114-120)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00021
Show More Cited By

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Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 17, Issue 3

July 2021

483 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3464978

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

Issue’s Table of Contents

Copyright © 2021 Association for Computing Machinery.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 11 May 2021

Accepted: 01 December 2020

Revised: 01 December 2020

Received: 01 June 2020

Published in JETC Volume 17, Issue 3

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Spanish Government
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P.O. FEDER of European Union
CSIC

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Cited By

He PBao TXie JAmin M(2023)FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum CryptographyACM Transactions on Reconfigurable Technology and Systems10.1145/356945716:3(1-23)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3569457
Khan SLee WKhalid AMajeed AHwang S(2023)Area-Optimized Constant-Time Hardware Implementation for Polynomial MultiplicationIEEE Embedded Systems Letters10.1109/LES.2022.318526515:1(5-8)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1109/LES.2022.3185265
He PBao TTu YXie J(2023)Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00021(114-120)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00021
Camacho-Ruiz ESánchez-Solano SMartínez-Rodríguez MTena-Sanchez EBrox P(2023)A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS58620.2023.10336001(1-6)Online publication date: 15-Nov-2023
https://doi.org/10.1109/DCIS58620.2023.10336001
Sánchez-Solano SCamacho-Ruiz EMartínez-Rodríguez MBrox P(2022)Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded SystemsSensors10.3390/s2205205722:5(2057)Online publication date: 7-Mar-2022
https://doi.org/10.3390/s22052057
Yang SLiu DHu ALi AZhang JLi XLu JMo C(2022)An Instruction-configurable Post-quantum Cryptographic Processor towards NTRU2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST56390.2022.10022178(1-6)Online publication date: 14-Dec-2022
https://doi.org/10.1109/AsianHOST56390.2022.10022178

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