An Ultra-wideband Limiting Amplifier for 15Gbps Receiver of JESD204B Physical Layer
Pages 132 - 139
Abstract
SerDes receivers are widely used in data converters and limiting amplifiers are widely used in the SerDes receivers. The paper presents the design of an ultra-wideband limiting amplifier applied to the receiver of JESD204B physical layer. This limiting amplifier adopts Current Mode Logic (CML) structure composed of three third-order stages for achieving the ultra-wide bandwidth with high gain. Feedback structure techniques, negative Miller capacitance techniques and inductor peaking techniques are implemented, which further increase bandwidth. On the other hand, this limiting amplifier could achieve equalizing easily for compensating for different channel loss. This limiting amplifier could work at the bit-rate of 15Gbps which fully reaches the highest data rate specified in the JESD204B standard. This limiting amplifier occupies area of 0.03mm2 and consumes a power of 21.6mW with a supply voltage 1.2V in TSMC 65nm CMOS technology.
References
[1]
JEDEC Standard JESD204B.01, January 2012.
[2]
P. Chokchalermwat and B. Supmonchai. 2018. Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers. In International Electrical Engineering Congress, (Krabi, Thailand, 2018). 1-4. Doi= http://10.1109/IEECON.2018.8712225.
[3]
M. Z. Khaki, M. Omoomi and E. Borzabadi, 2016.An ultra-low-power TIA plus limiting amplifier in 90nm CMOS technology for 2.5 Gb/s optical receiver. In 2016 24th Iranian Conference on Electrical Engineering (Shiraz, 2016). 1055-1059. Doi=http://10.1109/IranianCEE.2016.7585677.
[4]
S. Ray, A. Chowdhury and M. M. Hella. 2018. Enhancing the Stability of Broadband Amplifiers Using Third Order Nested Feedback. In 2018 IEEE International Symposium on Circuits and Systems (Florence, 2018). 1-4. Doi= http: //10.1109/ISCAS.2018.8351316.
[5]
M. Dongi and M. Jalali. 2017. A wideband CMOS VGA with dB-linear gain based on active feedback and negative capacitance. In 2017 Iranian Conference on Electrical Engineering (Tehran, 2017). 506-510. Doi=http: //10.1109/IranianCEE.2017.7985090.
[6]
S. Huang and W. Chen. 2013. A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS. In 2013 IEEE Asian Solid-State Circuits Conference (Singapore, 2013). 225-228. Doi= http: //10.1109/ASSCC.2013.6691023.
[7]
S. Galal and B. Razavi. 2003. 10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology. In IEEE Journal of Solid-State Circuits. (Dec. 2003). 2138-2146. Doi= http://0.1109/JSSC.2003.818567.
[8]
L. Chen, Z. Li and Z. Wang. A 10-Gb/s Inductorless CMOS Limiting Amplifier for Optic-Fiber Transmission System. In 2010 Symposium on Photonics and Optoelectronics (Chengdu, 2010). 1-4. Doi=http://10.1109/SOPO.2010.5504443.
[9]
K. Takano, R. Fujimoto, M. Motoyoshi, K. Katayama and M. Fujishima. 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. In 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. (Austin, TX, 2013). 135-137. Doi= http://10.1109/SiRF.2013.6489457.
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Published In
February 2021
336 pages
ISBN:9781450389365
DOI:10.1145/3458380
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Published: 23 September 2021
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ICDSP 2021
ICDSP 2021: 2021 5th International Conference on Digital Signal Processing
February 26 - 28, 2021
Chengdu, China
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