Cited By
View all- Mustafa DAlkhasawneh RObeidat FShatnawi A(2024)MIMD Programs Execution Support on SIMD Machines: A Holistic SurveyIEEE Access10.1109/ACCESS.2024.337299012(34354-34377)Online publication date: 2024
Adapting SYCL’s SIMT Programming Paradigm for Accelerators via Program Reconstruction
Article No.: 22, Pages 1 - 6
Abstract
We present an IR-to-IR Converter that is capable of converting from LLVM IR to Halide IR and MLIR’s Affine Dialect to support generation of high performance SYCL kernel code [10] targeting accelerators with explicit memory hierarchy design. The converter performs program reconstruction to raise abstraction of the IR. Once the IR is raised to the level of Halide IR, AKG [2] can be leveraged to generate performant DaVinci code [2]. Alternatively, when the IR is raised to MLIR’s Affine Dialect, existing MLIR Affine passes with minor modifications can be readily used. Subsequently, the IR is lowered back to LLVM IR through progressive lowering. LLVM’s LLC is used to create the final binary for both cases. We extend upon SYCL’s buffer, accessor and parallel_for abstractions to facilitate the IR raising process.
References
[1]
2015. LLVM Developers’ Meeting: Pierre-Andre Saulais “Creating an SPMD Vectorizer”. https://www.youtube.com/watch?v=ePu6c4FLc9I.
[2]
2021. Automatic Kernel Generator. https://gitee.com/mindspore/akg/.
[3]
2021. C Language Family Front-end. https://github.com/compiler-tree-technologies/cil/tree/cil/clang/.
[4]
2021. Cambricon MLU Hardware Architecture. https://www.cambricon.com/docs/bangc/developer_guide_html/3MLUhardwarearchitecture/index.html.
[5]
2021. Eigen 3.3.9. https://eigen.tuxfamily.org/.
[6]
2021. Intel’s LLVM Project. https://github.com/intel/llvm/.
[7]
2021. Multi-Level IR Compiler Framework. https://mlir.llvm.org/.
[8]
2021. An Optimized BLAS Library. https://www.openblas.net/.
[9]
2021. The Region Vectorizer (RV). https://github.com/cdl-saarland/rv.
[10]
2021. SYCL Khronos Group. https://khronos.org/sycl/.
[11]
Lorenzo Chelini, Andi Drebes, Oleksandr Zinenko, Albert Cohen, Nicolas Vasilache, Tobias Grosser, and Henk Corporaal. 2021. Progressive Raising in Multi-level IR. In 2021 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). 15–26. https://doi.org/10.1109/CGO51591.2021.9370332
[12]
Wilson Feng, Rasool Maghareh, and Kai-Ting Amy Wang. 2021. Extending DPC++ with Support for Huawei Ascend AI Chipset. In International Workshop on OpenCL(Munich, Germany) (IWOCL’21). Association for Computing Machinery, New York, NY, USA, Article 13, 4 pages. https://doi.org/10.1145/3456669.3456684
[13]
Tobias Grosser, Sebastian Pop, J Ramanujam, and P Sadayappan. 2015. On Recovering Multi-Dimensional Arrays in Polly. http://impact.gforge.inria.fr/impact2015/index.html Fifth International Workshop on Polyhedral Compilation Techniques, Impact 2015 ; Conference date: 19-01-2015 Through 19-01-2015.
[14]
Ralf Karrenberg and Sebastian Hack. 2011. Whole-function vectorization. In International Symposium on Code Generation and Optimization (CGO 2011). 141–150. https://doi.org/10.1109/CGO.2011.5764682
[15]
Heng Liao, Jiajin Tu, Jing Xia, and Xiping Zhou. 2019. DaVinci: A Scalable Architecture for Neural Network Computing. In 2019 IEEE Hot Chips 31 Symposium (HCS). 1–44. https://doi.org/10.1109/HOTCHIPS.2019.8875654
[16]
William S. Moses, Lorenzo Chelini, Ruizhe Zhao, and Oleksandr Zinenko. 2021. Polygeist: Affine C in MLIR. https://acohen.gitlabpages.inria.fr/impact/impact2021/papers/IMPACT_2021_paper_1.pdf Not a formal proceedings.
[17]
Maurice Peemen, Bart Mesman, and Henk Corporaal. 2015. Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition(Grenoble, France) (DATE ’15). EDA Consortium, San Jose, CA, USA, 169–174.
[18]
Matt Pharr and William Mark. 2012. ispc: A SPMD compiler for high-performance CPU programming. 2012 Innovative Parallel Computing, InPar 2012, 1–13. https://doi.org/10.1109/InPar.2012.6339601
[19]
Jie Zhao and Peng Di. 2020. Optimizing the Memory Hierarchy by Compositing Automatic Transformations on Computations and Data. In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 427–441. https://doi.org/10.1109/MICRO50266.2020.00044
Index Terms
- Adapting SYCL’s SIMT Programming Paradigm for Accelerators via Program Reconstruction
Index terms have been assigned to the content through auto-classification.
Recommendations
Early experiments using SYCL single-source modern C++ on Xilinx FPGA: Extended Abstract of Technical Presentation
IWOCL '18: Proceedings of the International Workshop on OpenCLHeterogeneous computing is required in systems ranging from low-end embedded systems up to the high-end HPC systems to reach high-performance while keeping power consumption low. Having more and more CPU and accelerators such as FPGA creates challenges ...
One Pass to Bind Them: The First Single-Pass SYCL Compiler with Unified Code Representation Across Backends
IWOCL '23: Proceedings of the 2023 International Workshop on OpenCLCurrent SYCL implementations rely on multiple compiler invocations to generate code for host and device, and typically even employ one compiler invocation per required backend code format such as SPIR-V, PTX or amdgcn. This makes generating “universal” ...
Black-Scholes Option Pricing on Intel CPUs and GPUs: Implementation on SYCL and Optimization Techniques
SupercomputingAbstractThe Black-Scholes option pricing problem is one of the widely used financial benchmarks. We explore the possibility of developing a high-performance portable code using the SYCL (Data Parallel C++) programming language. We start from a C++ code ...
Comments
Information & Contributors
Information
Published In
August 2021
314 pages
ISBN:9781450384414
DOI:10.1145/3458744
Copyright © 2021 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 23 September 2021
Check for updates
Author Tags
Qualifiers
- Article
- Research
- Refereed limited
Conference
ICPP 2021
Acceptance Rates
Overall Acceptance Rate 91 of 313 submissions, 29%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 806Total Downloads
- Downloads (Last 12 months)242
- Downloads (Last 6 weeks)25
Reflects downloads up to 30 Aug 2024
Other Metrics
Citations
Cited By
View all- Mustafa DAlkhasawneh RObeidat FShatnawi A(2024)MIMD Programs Execution Support on SIMD Machines: A Holistic SurveyIEEE Access10.1109/ACCESS.2024.337299012(34354-34377)Online publication date: 2024
View Options
View options
View or Download as a PDF file.
PDFeReader
View online with eReader.
eReaderHTML Format
View this article in HTML Format.
HTML FormatGet Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in