research-article

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Solver-Aided Constant-Time Hardware Verification

Authors:

Klaus v. Gleissenthall,

Rami Gökhan Kıcı,

Ranjit JhalaAuthors Info & Claims

CCS '21: Proceedings of the 2021 ACM SIGSAC Conference on Computer and Communications Security

Pages 429 - 444

https://doi.org/10.1145/3460120.3484810

Published: 13 November 2021 Publication History

Abstract

We present Xenon, a solver-aided, interactive method for formally verifying that Verilog hardware executes in constant-time. Xenon scales to realistic hardware designs by drastically reducing the effort needed to localize the root cause of verification failures via a new notion of constant-time counterexamples, which Xenon uses to synthesize a minimal set of secrecy assumptions in an interactive verification loop. To reduce verification time Xenon exploits modularity in Verilog code via module summaries, thereby avoiding duplicate work across multiple module instantiations. We show how Xenon's assumption synthesis and summaries enable us to verify different kinds of circuits, including a highly modular AES- 256 implementation where modularity cuts verification from six hours to under three seconds, and the ScarVside-channel hardened RISC-V micro-controller whose size exceeds previously verified designs by an order of magnitude. In a small study, we also find that Xenon helps non-expert users complete verification tasks correctly and faster than previous state-of-art tools.

References

[1]

[n.d.]. BearSSL - Constant-Time Crypto. https://www.bearssl.org/constanttime.html. (Accessed on 08/19/2020).

[2]

[n.d.]. fpga_mc/fpu at master ·monajalal/fpga_mc ·GitHub. https://github.com/monajalal/fpga_mc/tree/master/fpu. (Accessed on 08/16/2020).

[3]

[n.d.]. GitHub - dawsonjon/fpu: synthesiseable ieee 754 floating point library in verilog. https://github.com/dawsonjon/fpu. (Accessed on 08/16/2020).

[4]

[n.d.]. GitHub - scarv/scarv-cpu: SCARV: a side-channel hardened RISC-V platform. https://github.com/scarv/scarv-cpu. (Accessed on 08/16/2020).

[5]

[n.d.]. GitHub - scarv/xcrypto: XCrypto: a cryptographic ISE for RISC-V. https://github.com/scarv/xcrypto. (Accessed on 08/19/2020).

[6]

[n.d.]. GitHub - tommythorn/yarvi: Yet Another RISC-V Implementation. https://github.com/tommythorn/yarvi. (Accessed on 08/16/2020).

[7]

[n.d.]. GLPK - GNU Project - Free Software Foundation (FSF). https://www.gnu.org/software/glpk/. (Accessed on 08/10/2020).

[8]

[n.d.]. liquid-fixpoint: Horn Clause Constraint Solving for Liquid Types. https://github.com/ucsd-progsys/liquid-fixpoint. Accessed: 2018-08--29.

[9]

[n.d.]. MIPS. https://github.com/gokhankici/iodine/tree/master/benchmarks/472-mips-pipelined. (Accessed on 08/16/2020).

[10]

[n.d.]. Overview :: AES :: OpenCores. https://opencores.org/projects/tiny_aes. (Accessed on 08/05/2020).

[11]

[n.d.]. Overview :: SHA cores :: OpenCores. https://opencores.org/projects/sha_core. (Accessed on 08/16/2020).

[12]

[n.d.]. TIS-CT. http://trust-in-soft.com/tis-ct/.

[13]

2005. IEEE Standard for Verilog Hardware Description Language. IEEE Std 1364--2005.

[14]

Aws Albarghouthi, Isil Dillig, and Arie Gurfinkel. 2016. Maximal specification synthesis. In Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2016, St. Petersburg, FL, USA, January 20 - 22, 2016, Rastislav Bodík and Rupak Majumdar (Eds.). ACM, 789--801. https://doi.org/10.1145/2837614.2837628

Digital Library

[15]

José Bacelar Almeida, Manuel Barbosa, Gilles Barthe, François Dupressoir, and Michael Emmi. 2016. Verifying constant-time implementations. In USENIX Security Symposium.

[16]

José Bacelar Almeida, Manuel Barbosa, Gilles Barthe, François Dupressoir, and Michael Emmi. 2016. Verifying Constant-Time Implementations. In USENIX Security.

[17]

J Bacelar Almeida, Manuel Barbosa, Jorge S Pinto, and Bárbara Vieira. 2013. Formal verification of side-channel countermeasures using self-composition, In Science of Computer Programming. Science of Computer Programming.

[18]

Rajeev Alur and Thomas A. Henzinger. 1999. Reactive Modules. Formal Methods Syst. Des. 15, 1 (1999), 7--48. https://doi.org/10.1023/A:1008739929481

Digital Library

[19]

Marc Andrysco, David Kohlbrenner, Keaton Mowery, Ranjit Jhala, Sorin Lerner, and Hovav Shacham. 2015. On subnormal floating point and abnormal timing. In S&P.

[20]

Marc Andrysco, Andres Nötzli, Fraser Brown, Ranjit Jhala, and Deian Stefan. 2018. Towards Verified, Constant-time Floating Point Operations. In Proceedings of the ACM SIGSAC Conference on Computer and Communications Security. ACM.

Digital Library

[21]

Manuel Barbosa, Gilles Barthe, Karthikeyan Bhargavan, Bruno Blanchet, Cas Cremers, Kevin Liao, and Bryan Parno. 2021. SoK: Computer-Aided Cryptography. In IEEE Symposium on Security and Privacy.

[22]

Gilles Barthe, Gustavo Betarte, Juan Campo, Carlos Luna, and David Pichardie. 2014. System-level Non-interference for Constant-time Cryptography. In Proceedings of the ACM SIGSAC Conference on Computer and Communications Security. ACM.

Digital Library

[23]

Daniel J. Bernstein. 2005. Cache-timing attacks on AES. Technical Report. https://cr.yp.to/antiforgery/cachetiming-20050414.pdf

[24]

Nikolaj Bjørner, Arie Gurfinkel, Ken McMillan, and Andrey Rybalchenko. 2015. Horn Clause Solvers for Program Verification. In Fields of Logic and Computation.

[25]

Ferdinand Brasser, Urs Müller, Alexandra Dmitrienko, Kari Kostiainen, Srdjan Capkun, and Ahmad-Reza Sadeghi. 2017. Software grand exposure:SGX cache attacks are practical. In Workshop on Offensive Technologies.

[26]

David Brumley and Dan Boneh. 2005. Remote timing attacks are practical. Computer Networks (2005).

Digital Library

[27]

Cristiano Calcagno, Dino Distefano, Peter W. O'Hearn, and Hongseok Yang. [n.d.]. Compositional Shape Analysis by Means of Bi-Abduction. 58, 6 ([n. d.]), 26:1--26:66. https://doi.org/10.1145/2049697.2049700

Digital Library

[28]

Sunjay Cauligi, Craig Disselkoen, Klaus von Gleissenthall, Dean Tullsen, Deian Stefan, Tamara Rzk, and Gilles Barthe. 2020. Constant-time foundations for the new Spectre era. In Programming Language Design and Implementation (PLDI). ACM SIGPLAN.

[29]

Sunjay Cauligi, Gary Soeller, Brian Johannesmeyer, Fraser Brown, Riad S. Wahby, John Renner, Benjamin Gregoire, Gilles Barthe, Ranjit Jhala, and Deian Stefan. 2019. FaCT: A DSL for timing-sensitive computation. In Programming Language Design and Implementation (PLDI). ACM SIGPLAN.

[30]

Joonwon Choi, Muralidaran Vijayaraghavan, Benjamin Sherman, Adam Chlipala, and Arvind. 2017. Kami: A Platform for High-Level Parametric Hardware Specification and Its Modular Verification. In International Conference on Functional Programming (ICFP). ACM SIGPLAN. http://plv.csail.mit.edu/kami/papers/icfp17.pdf

[31]

Jürgen Christ, Evren Ermis, Martin Schäf, and Thomas Wies. 2013. Flow-Sensitive Fault Localization. Lecture Notes in Computer Science Verification, Model Checking, and Abstract Interpretation (2013), 189--208. https://doi.org/10.1007/978--3--642--35873--9_13

[32]

Michael R. Clarkson and Fred B. Schneider. 2010. Hyperproperties. Journal of Computer Security (2010).

Digital Library

[33]

Shaanan Cohney, Andrew Kwong, Shahar Paz, Daniel Genkin, Nadia Heninger, Eyal Ronen, and Yuval Yarom. 2020. Pseudorandom Black Swans: Cache Attacks on CTR_DRBG. In 2020 IEEE Symposium on Security and Privacy (SP). IEEE.

[34]

CHC competition (CHC-COMP). [n.d.]. .

[35]

Fergus Dall, Gabrielle De Micheli, Thomas Eisenbarth, Daniel Genkin, Nadia Heninger, Ahmad Moghimi, and Yuval Yarom. 2018. CacheQuote: Efficiently Recovering Long-term Secrets of SGX EPID via Cache Attacks. IACR Transactions on Cryptographic Hardware and Embedded Systems 2018, 2 (May 2018).

[36]

Lesly-Ann Daniel, Sébastien Bardin, and Tamara Rezk. 2020. BINSEC/REL: Efficient Relational Symbolic Execution for Constant-Time at Binary-Level. In IEEE Symposium on Security and Privacy.

[37]

Leonardo de Moura and Nikolaj Bjørner. 2008. Z3: An Efficient SMT Solver. In TACAS.

[38]

Isil Dillig, Thomas Dillig, and Alex Aiken. [n.d.]. Automated Error Diagnosis Using Abductive Inference. In Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2012-06--11) (PLDI '12). Association for Computing Machinery, 181--192. https://doi.org/10.1145/2254064.2254087

Digital Library

[39]

Isil Dillig, Thomas Dillig, Boyang Li, and Ken McMillan. 2013. Inductive Invariant Generation via Abductive Inference. SIGPLAN Not. 48, 10 (Oct. 2013), 443--456. https://doi.org/10.1145/2544173.2509511

Digital Library

[40]

Isil Dillig, Thomas Dillig, Boyang Li, Ken McMillan, and Mooly Sagiv. [n.d.]. Synthesis of Circular Compositional Program Proofs via Abduction. 19, 5 ([n. d.]), 535--547. https://doi.org/10.1007/s10009-015-0397--7

[41]

Goran Doychev, Dominik Feld, Boris Köpf, Laurent Mauborgne, and Jan Reineke. 2013. Cacheaudit: A tool for the static analysis of cache side channels. In USENIX Security.

[42]

Evren Ermis, Martin Schäf, and Thomas Wies. 2012. Error Invariants. FM 2012: Formal Methods Lecture Notes in Computer Science (Aug 2012), 187--201. https://doi.org/10.1007/978--3--642--32759--9_17

[43]

Mohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, and Wolfgang Kunz. 2020. A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors. In DAC.

[44]

Grigory Fedyukovich, Sumanth Prabhu, Kumar Madhukar, and Aarti Gupta. 2018. Solving Constrained Horn Clauses Using Syntax and Data. In FMCAD.

[45]

Andrew Ferraiuolo, Mark Zhao, Andrew C Myers, and G Edward Suh. 2018. HyperFlow: A processor architecture for nonmalleable, timing-safe information flow security. In SIGSAC.

[46]

Cormac Flanagan and K Rustan M Leino. [n.d.]. Houdini, an Annotation Assistant for ESC/Java. Springer, Berlin, Heidelberg, 500--517. https://doi.org/10.1007/3--540--45251--6_29

[47]

Pranav Garg, Christof Löding, P. Madhusudan, and Daniel Neider. 2014. ICE: A Robust Framework for Learning Invariants. Computer Aided Verification Lecture Notes in Computer Science (2014), 69--87. https://doi.org/10.1007/978--3--319-08867--9_5

[48]

Pranav Garg, Daniel Neider, P. Madhusudan, and Dan Roth. [n.d.]. Learning Invariants Using Decision Trees and Implication Counterexamples. In Principles of Programming Languages (New York, NY, USA, 2016-01--11) (POPL '16). ACM. https://doi.org/10.1145/2837614.2837664

Digital Library

[49]

Roberto Giacobazzi. [n.d.]. Abductive Analysis of Modular Logic Programs. In Proceedings of the 1994 International Symposium on Logic Programming (Cambridge, MA, USA, 1994--11-01) (ILPS '94). MIT Press, 377--391.

Digital Library

[50]

Klaus V. Gleissenthall, Rami Gökhan Kici, Deian Stefan, and Ranjit Jhala. 2019. IODINE: Verifying Constant-Time Execution of Hardware. In USENIX Conference on Security Symposium.

[51]

Michael J. C. Gordon. 1995. The semantic challenge of Verilog HDL. In LICS.

[52]

Sergey Grebenshchikov, Nuno P. Lopes, Corneliu Popeea, and Andrey Rybalchenko. 2012. Synthesizing software verifiers from proof rules. In PLDI.

[53]

Marco Guarnieri, Boris Koepf, Jan Reineke, and Pepe Vila. 2021. Hardware- Software Contracts for Secure Speculation. In S&P.

[54]

Anubhav Gupta, Kenneth L. McMillan, and Zhaohui Fu. 2008. Automated assumption generation for compositional verification. Formal Methods Syst. Des. 32, 3 (2008), 285--301. https://doi.org/10.1007/s10703-008-0050-0

Digital Library

[55]

Arie Gurfinkel, Temesghen Kahsai, Anvesh Komuravelli, and Jorge A. Navas. 2015. The SeaHorn Verification Framework. In CAV.

[56]

Andreas Haeberlen, Benjamin C. Pierce, and Arjun Narayan. 2011. Differential Privacy under Fire. In USENIX Security, David Wagner (Ed.).

[57]

Hossein Hojjat and Philipp Rümmer. 2018. The Eldarica Horn Solver. In FMCAD.

[58]

Ranjit Jhala, Andreas Podelski, and Andrey Rybalchenko. 2018. Predicate Abstraction for Program Verification. Springer International Publishing, Cham, 447--491. https://doi.org/10.1007/978--3--319--10575--8_15

[59]

Manu Jose and Rupak Majumdar. [n.d.]. Bug-Assist: Assisting Fault Localization in ANSI-C Programs. In Computer Aided Verification (Berlin, Heidelberg, 2011) (Lecture Notes in Computer Science), Ganesh Gopalakrishnan and Shaz Qadeer (Eds.). Springer, 504--509. https://doi.org/10.1007/978--3--642--22110--1_40

[60]

Manu Jose and Rupak Majumdar. 2011. Cause clue clauses. Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation - PLDI 11 (2011). https://doi.org/10.1145/1993498.1993550

Digital Library

[61]

Rami Gökhan Kici. 2020. Personal communication.

[62]

Paul C Kocher. 1996. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In CRYPTO.

[63]

David Kohlbrenner and Hovav Shacham. 2017. On the effectiveness of mitigations against floating-point timing channels. In USENIX Security.

[64]

Hyoukjun Kwon, William Harris, and Hadi Esameilzadeh. 2017. Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants. In CSF.

[65]

Adam Langley. [n.d.]. ctgrind: Checking that functions are constant time with Valgrind. https://github.com/agl/ctgrind/.

[66]

Xun Li, Mohit Tiwari, Jason K Oberg, Vineeth Kashyap, Frederic T Chong, Timothy Sherwood, and Ben Hardekopf. 2011. Caisson: a hardware description language for secure information flow. In PLDI.

[67]

Chang Liu, Austin Harris, Martin Maas, Michael Hicks, Mohit Tiwari, and Elaine Shi. 2015. Ghostrider: A hardware-software system for memory trace oblivious computation. SIGPLAN Notices (2015).

[68]

V. Benjamin Livshits, Aditya V. Nori, Sriram K. Rajamani, and Anindya Banerjee. 2009. Merlin: specification inference for explicit information flow problems. In Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2009, Dublin, Ireland, June 15--21, 2009, Michael Hind and Amer Diwan (Eds.). ACM, 75--86. https://doi.org/10.1145/1542476.1542485

Digital Library

[69]

Kenneth L. McMillan. 1997. A Compositional Rule for Hardware Design Refinement. In Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22--25, 1997, Proceedings (Lecture Notes in Computer Science), Orna Grumberg (Ed.), Vol. 1254. Springer, 24--35. https://doi.org/10.1007/3--540--63166--6_6

[70]

Daniel Moghimi, Berk Sunar, Thomas Eisenbarth, and Nadia Heninger. 2020. TPM-FAIL:TPM meets Timing and Lattice Attacks. In USENIX Security.

[71]

Dag Arne Osvik, Adi Shamir, and Eran Tromer. 2006. Cache attacks and countermeasures: the case of AES. In Cryptographers' Track at the RSA Conference. Springer.

Digital Library

[72]

Saswat Padhi, Rahul Sharma, and Todd Millstein. [n.d.]. Data-driven precondition inference with learned features. In Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2016-06-02) (PLDI '16). Association for Computing Machinery, 42--56. https://doi.org/10.1145/2908080.2908099

Digital Library

[73]

Christos H. Papadimitriou and Kenneth Steiglitz. 1982. Combinatorial Optimization: Algorithms and Complexity. Prentice-Hall, Inc., USA.

Digital Library

[74]

Sumanth Prabhu, Grigory Fedyukovich, Kumar Madhukar, and Deepak D'Souza. 2021. Specification Synthesis with Constrained Horn Clauses. In PLDI.

[75]

Ashay Rane, Calvin Lin, and Mohit Tiwari. 2015. Raccoon: Closing Digital Side-Channels through Obfuscated Execution. In USENIX Security.

[76]

Ashay Rane, Calvin Lin, and Mohit Tiwari. 2016. Secure, Precise, and Fast Floating-Point Operations on x86 Processors. In USENIX Security.

[77]

Oscar Reparaz, Joseph Balasch, and Ingrid Verbauwhede. 2017. Dude, is my code constant time?. In DATE.

[78]

Thomas W. Reps, Susan Horwitz, and Shmuel Sagiv. 1995. Precise Interprocedural Dataflow Analysis via Graph Reachability. In Conference Record of POPL'95: 22nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, San Francisco, California, USA, January 23--25, 1995, Ron K. Cytron and Peter Lee (Eds.). ACM Press, 49--61. https://doi.org/10.1145/199448.199462

Digital Library

[79]

Bruno Rodrigues, Fernando Magno Quintão Pereira, and Diego F Aranha. 2016. Sparse representation of implicit flows with applications to side-channel detection. In CCC.

[80]

Xujie Si, Hanjun Dai, Mukund Raghothaman, Mayur Naik, and Le Song. [n.d.]. Learning Loop Invariants for Program Verification. In Advances in Neural Information Processing Systems 31, S. Bengio, H. Wallach, H. Larochelle, K. Grauman, N. Cesa-Bianchi, and R. Garnett (Eds.). Curran Associates, Inc., 7751--7762. http://papers.nips.cc/paper/8001-learning-loop-invariants-for-program-verification.pdf

[81]

Xujie Si, Aaditya Naik, Hanjun Dai, Mayur Naik, and Le Song. [n.d.]. Code2Inv: A Deep Learning Framework for Program Verification. In Computer Aided Verification (Cham, 2020) (Lecture Notes in Computer Science), Shuvendu K. Lahiri and Chao Wang (Eds.). Springer International Publishing, 151--164. https://doi.org/10.1007/978--3-030--53291--8_9

[82]

Mohit Tiwari, Jason K Oberg, Xun Li, Jonathan Valamehr, Timothy Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, and Timothy Sherwood. 2011.Crafting a Usable Microkernel, Processor, and I/O System with Strict and Provable Information Flow Security. In ISCA.

[83]

Mohit Tiwari, Hassan MG Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T Chong, and Timothy Sherwood. 2009. Complete information flow tracking from the gates up. In Sigplan Notices.

[84]

Muralidaran Vijayaraghavan, Adam Chlipala, Arvind, and Nirav Dave. [n.d.]. Modular Deductive Verification of Multiprocessor Hardware Designs. In Computer Aided Verification (Cham, 2015) (Lecture Notes in Computer Science), Daniel Kroening and Corina S. P's?reanu (Eds.). Springer International Publishing, 109--127. https://doi.org/10.1007/978--3--319--21668--3_7

[85]

Conrad Watt, John Renner, Natalie Popescu, Sunjay Cauligi, and Deian Stefan. 2019. CT-Wasm: Type-driven Secure Cryptography for the Web Ecosystem. POPL.

[86]

W. Eric Wong, Ruizhi Gao, Yihao Li, Rui Abreu, and Franz Wotawa. 2016. A Survey on Software Fault Localization. IEEE Transactions on Software Engineering 42, 8 (2016), 707--740. https://doi.org/10.1109/tse.2016.2521368

Digital Library

[87]

Yuan Xiao, Mengyuan Li, Sanchuan Chen, and Yinqian Zhang. 2017. STACCO: Differentially analyzing side-channel traces for detecting SSL/TLS vulnerabilities in secure enclaves. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security. 859--874.

Digital Library

[88]

Yuval Yarom, Daniel Genkin, and Nadia Heninger. 2017. CacheBleed: a timing attack on OpenSSL constant-time RSA. Journal of Cryptographic Engineering 7, 2 (2017), 99--112.

[89]

Jiyong Yu, Lucas Hsiung, Mohamad El Hajj, and Christopher W Fletcher. 2019. Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing. In NDSS.

[90]

Danfeng Zhang, Aslan Askarov, and Andrew C. Myers. 2012. Language-based control and mitigation of timing channels. In PLDI.

[91]

Danfeng Zhang, Yao Wang, G. Edward Suh, and Andrew C. Myers. 2015. A Hardware Design Language for Timing-Sensitive Information-Flow Security. In ASPLOS.

[92]

Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, and Sharad Malik. [n.d.]. Synthesizing Environment Invariants for Modular Hardware Verification. In Verification, Model Checking, and Abstract Interpretation (Cham, 2020) (Lecture Notes in Computer Science), Dirk Beyer and Damien Zufferey (Eds.). Springer International Publishing, 202--225. https://doi.org/10.1007/978--3-030--39322--9_10

Digital Library

Cited By

Deutschmann LKazhalawi YSeckinger JAntón AMüller JFadiheh MStoffel DKunz W(2024)Data-Oblivious and Performant: On Designing Security-Conscious Hardware2024 IEEE 25th Latin American Test Symposium (LATS)10.1109/LATS62223.2024.10534597(1-6)Online publication date: 9-Apr-2024
https://doi.org/10.1109/LATS62223.2024.10534597
Chakraborty PSuha TBhunia S(2023)Hardware Specification Aware Timing Side Channel Security Analysis2023 IEEE 36th International System-on-Chip Conference (SOCC)10.1109/SOCC58585.2023.10256749(1-6)Online publication date: 5-Sep-2023
https://doi.org/10.1109/SOCC58585.2023.10256749
Baty MWilke PHiet GFontaine ATrieu A(2023)A Generic Framework to Develop and Verify Security Mechanisms at the Microarchitectural Level: Application to Control-Flow Integrity2023 IEEE 36th Computer Security Foundations Symposium (CSF)10.1109/CSF57540.2023.00029(372-387)Online publication date: Jul-2023
https://doi.org/10.1109/CSF57540.2023.00029
Show More Cited By

Index Terms

Solver-Aided Constant-Time Hardware Verification
1. Security and privacy
  1. Formal methods and theory of security
    1. Logic and verification
  2. Security in hardware
    1. Hardware attacks and countermeasures
      1. Side-channel analysis and countermeasures

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cover image ACM Conferences

CCS '21: Proceedings of the 2021 ACM SIGSAC Conference on Computer and Communications Security

November 2021

3558 pages

ISBN:9781450384544

DOI:10.1145/3460120

General Chairs:
Yongdae Kim
KAIST, Republic of Korea
,
Jong Kim
POSTECH, Republic of Korea
,
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Giovanni Vigna
University of California, Santa Barbara / VMware, USA
,
Elaine Shi
Carnegie Mellon University, USA

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Cited By

Deutschmann LKazhalawi YSeckinger JAntón AMüller JFadiheh MStoffel DKunz W(2024)Data-Oblivious and Performant: On Designing Security-Conscious Hardware2024 IEEE 25th Latin American Test Symposium (LATS)10.1109/LATS62223.2024.10534597(1-6)Online publication date: 9-Apr-2024
https://doi.org/10.1109/LATS62223.2024.10534597
Chakraborty PSuha TBhunia S(2023)Hardware Specification Aware Timing Side Channel Security Analysis2023 IEEE 36th International System-on-Chip Conference (SOCC)10.1109/SOCC58585.2023.10256749(1-6)Online publication date: 5-Sep-2023
https://doi.org/10.1109/SOCC58585.2023.10256749
Baty MWilke PHiet GFontaine ATrieu A(2023)A Generic Framework to Develop and Verify Security Mechanisms at the Microarchitectural Level: Application to Control-Flow Integrity2023 IEEE 36th Computer Security Foundations Symposium (CSF)10.1109/CSF57540.2023.00029(372-387)Online publication date: Jul-2023
https://doi.org/10.1109/CSF57540.2023.00029
Ammanaghatta Shivakumar BBarthe GGrégoire BLaporte VPriya SYin HStavrou ACremers CShi E(2022)Enforcing Fine-grained Constant-time PoliciesProceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security10.1145/3548606.3560689(83-96)Online publication date: 7-Nov-2022
https://dl.acm.org/doi/10.1145/3548606.3560689

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