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BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications

Published: 11 January 2022 Publication History

Abstract

“Cloud-native” is the umbrella adjective describing the standard approach for developing applications that exploit cloud infrastructures’ scalability and elasticity at their best. As the application complexity and user-bases grow, designing for performance becomes a first-class engineering concern. As an answer to these needs, heterogeneous computing platforms gained widespread attention as powerful tools to continue meeting SLAs for compute-intensive cloud-native workloads. We propose BlastFunction, an FPGA-as-a-Service full-stack framework to ease FPGAs’ adoption for cloud-native workloads, integrating with the vast spectrum of fundamental cloud models. At the IaaS level, BlastFunction time-shares FPGA-based accelerators to provide multi-tenant access to accelerated resources without any code rewriting. At the PaaS level, BlastFunction accelerates functionalities leveraging the serverless model and scales functions proactively, depending on the workload’s performance. Further lowering the FPGAs’ adoption barrier, an accelerators’ registry hosts accelerated functions ready to be used within cloud-native applications, bringing the simplicity of a SaaS-like approach to the developers. After an extensive experimental campaign against state-of-the-art cloud scenarios, we show how BlastFunction leads to higher performance metrics (utilization and throughput) against native execution, with minimal latency and overhead differences. Moreover, the scaling scheme we propose outperforms the main serverless autoscaling algorithms in workload performance and scaling operation amount.

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  1. BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications

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        Published In

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 15, Issue 2
        June 2022
        310 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/3501287
        • Editor:
        • Deming Chen
        Issue’s Table of Contents

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 11 January 2022
        Accepted: 01 June 2021
        Revised: 01 May 2021
        Received: 01 January 2021
        Published in TRETS Volume 15, Issue 2

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        Author Tags

        1. Field Programmable Gate Arrays (FPGAs)
        2. cloud-native
        3. time-sharing
        4. autoscaling
        5. hardware acceleration

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        • (2022)Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research StudiesIEEE Access10.1109/ACCESS.2022.319491310(79825-79873)Online publication date: 2022
        • (2022)Machine Learning for Agile FPGA DesignMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_16(471-504)Online publication date: 10-Aug-2022
        • (2021)The Future of High-Performance Computing2021 17th International Computer Engineering Conference (ICENCO)10.1109/ICENCO49852.2021.9698918(129-134)Online publication date: 29-Dec-2021

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