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PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA

Authors:

Dhananjaya Wijerathne,

Thilini Kaushalya Bandara,

Tulika MitraAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 127 - 132

https://doi.org/10.1145/3489517.3530429

Published: 23 August 2022 Publication History

Abstract

CGRAs are well-suited as hardware accelerators due to power efficiency and reconfigurability. However, their potential is limited by the inability of the compiler to map complex loop kernels onto the architectures effectively. We propose PANORAMA, a fast and scalable compiler based on a divide-and-conquer approach to generate quality mapping for complex dataflow graphs (DFG) representing loop bodies onto larger CGRAs. PANORAMA improves the throughput of the mapped loops by up to 2.6x with 8.7x faster compilation time compared to the state-of-the-art techniques.

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Cited By

Chen SCai CZheng SLi JZhu GLi JYan YDai YYin WWang L(2024)HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space ExplorationACM Transactions on Reconfigurable Technology and Systems10.1145/365617617:2(1-31)Online publication date: 10-May-2024
https://dl.acm.org/doi/10.1145/3656176
Qiu YMao YGao XChen SLi JYin WWang L(2024)FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level ParallelismACM Transactions on Reconfigurable Technology and Systems10.1145/361422417:1(1-26)Online publication date: 27-Jan-2024
https://dl.acm.org/doi/10.1145/3614224
Chong YHarish RPanicker RNambiar VDo A(2024)A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558192(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558192
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Published In

cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 Owner/Author.

This work is licensed under a Creative Commons Attribution International 4.0 License.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 August 2022

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DAC '22

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SIGDA

DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Chen SCai CZheng SLi JZhu GLi JYan YDai YYin WWang L(2024)HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space ExplorationACM Transactions on Reconfigurable Technology and Systems10.1145/365617617:2(1-31)Online publication date: 10-May-2024
https://dl.acm.org/doi/10.1145/3656176
Qiu YMao YGao XChen SLi JYin WWang L(2024)FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level ParallelismACM Transactions on Reconfigurable Technology and Systems10.1145/361422417:1(1-26)Online publication date: 27-Jan-2024
https://dl.acm.org/doi/10.1145/3614224
Chong YHarish RPanicker RNambiar VDo A(2024)A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558192(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558192
Hassan ZOmetov ALohan ENurmi J(2024)Coarse-grained reconfigurable architectures for radio baseband processing: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103243154(103243)Online publication date: Sep-2024
https://doi.org/10.1016/j.sysarc.2024.103243
Wu DChen PBandara TLi ZMitra T(2023)Flip: Data-centric Edge CGRA AcceleratorACM Transactions on Design Automation of Electronic Systems10.1145/363111829:1(1-25)Online publication date: 18-Dec-2023
https://dl.acm.org/doi/10.1145/3631118
Ni XGe MTao YSun WDuan FBai XXu QChen SKang Y(2023)BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable ArrayIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.325368670:8(3054-3058)Online publication date: Aug-2023
https://doi.org/10.1109/TCSII.2023.3253686
Wu HLi WFan ZWang ZLiu THuang JTang SLiu YZhang KYe XFan D(2023)Alleviating Transfer Latency in DataFlow Accelerator for DSP Applications2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00073(440-443)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00073
Zhuang JYang ZZhou P(2023)High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247981(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247981
Aghapour EZhang YPathania AMitra T(2023)Pipelined CNN Inference on Heterogeneous Multi-processor System-on-ChipEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_16(405-427)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_16
Li ZWijerathne DMitra T(2022)Coarse-Grained Reconfigurable Array (CGRA)Handbook of Computer Architecture10.1007/978-981-15-6401-7_50-1(1-41)Online publication date: 25-Nov-2022
https://doi.org/10.1007/978-981-15-6401-7_50-1

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