research-article

Enzian: an open, general, CPU/FPGA platform for systems software research

Authors:

Abishek Ramdas,

Michael Giardino,

Dario Korolija,

Melissa Licciardello,

Kristina Martsenko,

Reto Achermann,

Gustavo Alonso,

Timothy RoscoeAuthors Info & Claims

ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

Pages 434 - 451

https://doi.org/10.1145/3503222.3507742

Published: 22 February 2022 Publication History

Abstract

Hybrid computing platforms, comprising CPU cores and FPGA logic, are increasingly used for accelerating data-intensive workloads in cloud deployments, and are a growing topic of interest in systems research. However, from a research perspective, existing hardware platforms are limited: they are often optimized for concrete, narrow use-cases and, therefore lack the flexibility needed to explore other applications and configurations.

We show that a research group can design and build a more general, open, and affordable hardware platform for hybrid systems research. The platform, Enzian, is capable of duplicating the functionality of existing CPU/FPGA systems with comparable performance but in an open, flexible system. It couples a large FPGA with a server-class CPU in an asymmetric cache-coherent NUMA system. Enzian also enables research not possible with existing hybrid platforms, through explicit access to coherence messages, extensive thermal and power instrumentation, and an open, programmable baseboard management processor.

Enzian is already being used in multiple projects, is open source (both hardware and software), and available for remote use. We present the design principles of Enzian, the challenges in building it, and evaluate it with a range of existing research use-cases alongside other, more specialized platforms, as well as demonstrating research not possible on existing platforms.

References

[1]

Alibaba Cloud Services. 2020. Compute optimized instance families with FPGAs. https://www.alibabacloud.com/help/doc-detail/108504.htm

[2]

Gustavo Alonso, Timothy Roscoe, David Cock, Mohsen Owaida, Kaan Kara, Dario Korolija, David Sidler, and Zeke Wang. 2020. Tackling Hardware/Software co-design from a database perspective. In Proceedings of the 6th biennial Conference on Innovative Data Systems Research (CIDR). Amsterdam, Netherlands.

[3]

2019. ADM-PCIE-7V3 Datasheet. https://www.alpha-data.com/pdfs/adm-pcie-7v3.pdf

[4]

Jeff Barr. 2016. Developer Preview – EC2 Instances (F1) with Programmable Hardware. Amazon AWS. https://aws.amazon.com/blogs/aws/developer-preview-ec2-instances-f1-with-programmable-hardware/

[5]

Thomas Burd, Noah Beck, Sean White, Milam Paraschou, Nathan Kalyanasundharam, Gregg Donley, Alan Smith, Larry Hewitt, and Samuel Naffziger. 2018. Zeppelin: An SoC for Multichip Architectures. IEEE Journal of Solid-State Circuits, 54, 1 (2018), 133–143.

[6]

Matthew Burke, Sowmya Dharanipragada, Shannon Joyner, Adriana Szekeres, Jacob Nelson, Irene Zhang, and Dan R. K. Ports. 2021. PRISM: Rethinking the RDMA Interface for Distributed Systems. In Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles (SOSP ’21). Association for Computing Machinery, New York, NY, USA. 228–242. isbn:9781450387095 https://doi.org/10.1145/3477132.3483587

Digital Library

[7]

Anthony M. Cabrera and Roger D. Chamberlain. 2019. Exploring Portability and Performance of OpenCL FPGA Kernels on Intel HARPv2. In Proceedings of the International Workshop on OpenCL (IWOCL’19). Association for Computing Machinery, New York, NY, USA. Article 3, 10 pages. isbn:9781450362306 https://doi.org/10.1145/3318170.3318180

Digital Library

[8]

Irina Calciu, M. Talha Imran, Ivan Puddu, Sanidhya Kashyap, Hasan Al Maruf, Onur Mutlu, and Aasheesh Kolli. 2021. Rethinking Software Runtimes for Disaggregated Memory. In Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021). Association for Computing Machinery, New York, NY, USA. 79–92. isbn:9781450383172 https://doi.org/10.1145/3445814.3446713

Digital Library

[9]

Irina Calciu, Ivan Puddu, Aasheesh Kolli, Andreas Nowatzyk, Jayneel Gandhi, Onur Mutlu, and Pratap Subrahmanyam. 2019. Project PBerry: FPGA Acceleration for Remote Memory. In Proceedings of the Workshop on Hot Topics in Operating Systems (HotOS ’19). Association for Computing Machinery, New York, NY, USA. 127–135. isbn:9781450367271 https://doi.org/10.1145/3317550.3321424

Digital Library

[10]

Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, and Doug Burger. 2016. A Cloud-Scale Acceleration Architecture. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Article 7, 13 pages.

Digital Library

[11]

CCIX Consortium and others. 2019. Cache Coherent Interconnect for Accelerators (CCIX). http://www.ccixconsortium.com

[12]

Kevin K. Chang, A. Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O’Connor, Hasan Hassan, and Onur Mutlu. 2017. Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. Proc. ACM Meas. Anal. Comput. Syst., 1, 1 (2017), Article 10, June, 42 pages. https://doi.org/10.1145/3084447

Digital Library

[13]

Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, and Peng Wei. 2016. A Quantitative Analysis on Microarchitectures of Modern CPU-FPGA Platforms. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE Press, 1–6. https://doi.org/10.1145/2897937.2897972

Digital Library

[14]

Young-Kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, and Peng Wei. 2019. In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms. ACM Trans. Reconfigurable Technol. Syst., 12, 1 (2019), Article 4, Feb., 20 pages. issn:1936-7406 https://doi.org/10.1145/3294054

Digital Library

[15]

Eric Chung, Jeremy Fowers, Kalin Ovtcharov, Michael Papamichael, Adrian Caulfield, Todd Massengill, Ming Liu, Mahdi Ghandi, Daniel Lo, Steve Reinhardt, Shlomi Alkalay, Hari Angepat, Derek Chiou, Alessandro Forin, Doug Burger, Lisa Woods, Gabriel Weisz, Michael Haselman, and Dan Zhang. 2018. Serving DNNs in Real Time at Datacenter Scale with Project Brainwave. IEEE Micro, 38 (2018), March, 8–20. https://www.microsoft.com/en-us/research/publication/serving-dnns-real-time-datacenter-scale-project-brainwave/

[16]

Darren Cofer, Andrew Gacek, John Backes, Michael W. Whalen, Lee Pike, Adam Foltzer, Michal Podhradsky, Gerwin Klein, Ihor Kuz, June Andronick, Gernot Heiser, and Douglas Stuart. 2018. A Formal Approach to Constructing Secure Air Vehicle Software. Computer, 51, 11 (2018), 14–23. https://doi.org/10.1109/MC.2018.2876051

Digital Library

[17]

Lukas Convent, Sebastian Hungerecker, Torben Scheffel, Malte Schmitz, Daniel Thoma, and Alexander Weiss. 2018. Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing. In Runtime Verification, Christian Colombo and Martin Leucker (Eds.). Springer International Publishing, Cham. 43–63. isbn:978-3-030-03769-7

[18]

Louise Helen Crockett, Ross Elliot, Martin Enderwitz, and Robert Stewart. 2014. The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC. Strathclyde Academic Media.

Digital Library

[19]

CXL Consortium. 2020. Compute Express Link. https://www.computeexpresslink.org/

[20]

devicetree.org. 2020. Devicetree Specification (release v0.3 ed.). https://www.devicetree.org/specifications

[21]

Enzian Team. 2021. ASPLOS 2022 - Artifact. https://doi.org/10.5281/zenodo.5729174

[22]

Enzian Team. 2021. Enzian Board Design Files. https://doi.org/10.5281/zenodo.5802292

Digital Library

[23]

Tian Fang. 2014. Introducing “OpenBMC": an open software framework for next-generation system management. Facebook Engineering. https://engineering.fb.com/open-source/introducing-openbmc-an-open-software-framework-for-next-generation-system-management/

[24]

Daniel Firestone, Andrew Putnam, Sambhrama Mundkur, Derek Chiou, Alireza Dabagh, Mike Andrewartha, Hari Angepat, Vivek Bhanu, Adrian Caulfield, Eric Chung, Harish Kumar Chandrappa, Somesh Chaturmohta, Matt Humphrey, Jack Lavier, Norman Lam, Fengfen Liu, Kalin Ovtcharov, Jitu Padhye, Gautham Popuri, Shachar Raindel, Tejas Sapre, Mark Shaw, Gabriel Silva, Madhan Sivakumar, Nisheeth Srivastava, Anshuman Verma, Qasim Zuhair, Deepak Bansal, Doug Burger, Kushagra Vaid, David A. Maltz, and Albert Greenberg. 2018. Azure Accelerated Networking: SmartNICs in the Public Cloud. In Proceedings of the 15th USENIX Conference on Networked Systems Design and Implementation (NSDI’18). USENIX Association, USA. 51–64. isbn:9781931971430

[25]

Jeremy Fowers, Kalin Ovtcharov, Michael Papamichael, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, Michael Haselman, Logan Adams, Mahdi Ghandi, Stephen Heil, Prerak Patel, Adam Sapek, Gabriel Weisz, Lisa Woods, Sitaram Lanka, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, and Doug Burger. 2018. A Configurable Cloud-Scale DNN Processor for Real-Time AI. In Proceedings of the 45th Annual International Symposium on Computer Architecture (ISCA ’18). IEEE Press, 1–14. isbn:9781538659847 https://doi.org/10.1109/ISCA.2018.00012

Digital Library

[26]

Sara Hooker. 2021. The Hardware Lottery. Commun. ACM, 64, 12 (2021), nov, 58–65. issn:0001-0782

[27]

Lukas Humbel, Daniel Schwyn, Nora Hossle, Roni Haecki, Melissa Licciardello, Jan Schaer, David Cock, Michael Giardino, and Timothy Roscoe. 2021. A Model-Checked I^2C Specification. In International Symposium on Model Checking Software. 177–193. isbn:978-3-030-84629-9 https://doi.org/10.1007/978-3-030-84629-9_10

Digital Library

[28]

2016. Tofino. https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/tofino-series/tofino.html

[29]

2019. Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. MNL-1092, https://www.intel.com/content/www/us/en/programmable/documentation/buf1506187769663.html

[30]

2019. Intel FPGA Programmable Acceleration Card D5005 Data Sheet (ds-1058 ed.). https://www.intel.com/content/www/us/en/programmable/documentation/cvl1520030638800.html

[31]

Wenqi Jiang, Zhenhao He, Shuai Zhang, Kai Zeng, Liang Feng, Jiansong Zhang, Tongxuan Liu, Yong Li, Jingren Zhou, Ce Zhang, and Gustavo Alonso. 2021. FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters. In KDD ’21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining.

Digital Library

[32]

Kaan Kara, Jana Giceva, and Gustavo Alonso. 2017. FPGA-based Data Partitioning. In Proceedings of the 2017 ACM International Conference on Management of Data, SIGMOD Conference 2017.

Digital Library

[33]

Antoine Kaufmann, Simon Peter, Naveen Kr. Sharma, Thomas Anderson, and Arvind Krishnamurthy. 2016. High Performance Packet Processing with FlexNIC. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’16). Association for Computing Machinery, New York, NY, USA. 67–81. isbn:9781450340915 https://doi.org/10.1145/2872362.2872367

Digital Library

[34]

Ahmed Khawaja, Joshua Landgraf, Rohith Prakash, Michael Wei, Eric Schkufza, and Christopher J. Rossbach. 2018. Sharing, Protection, and Compatibility for Reconfigurable Fabric with AmorphOS. In Proceedings of the 13th USENIX Conference on Operating Systems Design and Implementation (OSDI’18). USENIX Association, USA. 107–127. isbn:9781931971478

[35]

Gerwin Klein, Kevin Elphinstone, Gernot Heiser, June Andronick, David Cock, Philip Derrin, Dhammika Elkaduwe, Kai Engelhardt, Rafal Kolanski, Michael Norrish, Thomas Sewell, Harvey Tuch, and Simon Winwood. 2009. SeL4: Formal Verification of an OS Kernel. In Proceedings of the ACM SIGOPS 22nd Symposium on Operating Systems Principles (SOSP ’09). Association for Computing Machinery, New York, NY, USA. 207–220. isbn:9781605587523 https://doi.org/10.1145/1629575.1629596

Digital Library

[36]

Jinhyung Koo, Junsu Im, Jooyoung Song, Juhyung Park, Eunji Lee, Bryan S. Kim, and Sungjin Lee. 2021. Modernizing File System through In-Storage Indexing. In 15th USENIX Symposium on Operating Systems Design and Implementation (OSDI 21). USENIX Association, 75–92. isbn:978-1-939133-22-9 https://www.usenix.org/conference/osdi21/presentation/koo

[37]

Dario Korolija, Dimitris Koutsoukos, Kimberly Keeton, Konstantin Taranov, Dejan Milojicic, and Gustavo Alonso. 2022. Farview: Disaggragated Memory with operator Off-loading for Database Engines. In Proceedings of the Conference on Innovative Data Systems Research (CIDR). Santa Cruz, CA, USA.

[38]

Dario Korolija, Timothy Roscoe, and Gustavo Alonso. 2020. Do OS abstractions make sense on FPGAs? In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). USENIX Association, 991–1010. isbn:978-1-939133-19-9 https://www.usenix.org/conference/osdi20/presentation/roscoe

[39]

Nikita Lazarev, Shaojie Xiang, neil Adit, Zhiru Zahng, and Christina Delimitrou. 2021. Dagger: Efficient and Fast RPCs in Cloud Microservices with Near-Memory Reconfigurable NICs. In ASPLOS.

[40]

Bojie Li, Zhenyuan Ruan, Wencong Xiao, Yuanwei Lu, Yongqiang Xiong, Andrew Putnam, Enhong Chen, and Lintao Zhang. 2017. KV-Direct: High-Performance In-Memory Key-Value Store with Programmable NIC. In SOSP.

[41]

Linux Kernel Documentation. 2019. Device Tree Source Format (version 1.0 ed.). https://git.kernel.org/pub/scm/utils/dtc/dtc.git/plain/Documentation/dts-format.txt

[42]

Jiacheng Ma, Gefei Zuo, Kevin Loughlin, Xiaohe Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, and Baris Kasikci. 2020. A Hypervisor for Shared-Memory FPGA Platforms. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’20). Association for Computing Machinery, New York, NY, USA. 827–844. isbn:9781450371025 https://doi.org/10.1145/3373376.3378482

Digital Library

[43]

Jakob Meier. 2020. Tools for Cache Coherence Protocol Interoperability. Master’s thesis. Department of Computer Science, ETH Zurich.

[44]

Mellanox. 2020. Mellanox Innova™ -2 FlexOpen Programmable SmartNIC. https://www.mellanox.com/files/doc-2020/pb-innova-2-flex.pdf

[45]

Jeffrey C. Mogul, Andrew Baumann, Timothy Roscoe, and Livio Soares. 2011. Mind the Gap: Reconnecting Architecture and OS Research. In Proceedings of the 13th USENIX Conference on Hot Topics in Operating Systems (HotOS’13). USENIX Association, USA. 1.

[46]

Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, and José F. Martínez. 2013. Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA ’13). Association for Computing Machinery, New York, NY, USA. 48–59. isbn:9781450320795 https://doi.org/10.1145/2485922.2485927

Digital Library

[47]

Alexey Natekin and Alois Knoll. 2013. Gradient Boosting Machines, A Tutorial. Frontiers in neurorobotics, 21.

[48]

NetFPGA. 2021. The NetFPGA Project. https://netfpga.org/

[49]

Cavium (now Marvell). 2017. Cavium ThunderX CN88XX, Pass 2. Document number CN88XX-HM-2.7P.

[50]

Cavium (now Marvell). 2017. ThunderX Family of Workload Optimized ARMv8 Processors. https://www.marvell.com/server-processors/thunderx-arm-processors/

[51]

Neal Oliver, Rahul R. Sharma, Stephen Chang, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra, Arthur Sheiman, Tim Whisonant, and Prabhat Gupta. 2011. A Reconfigurable Computing System Based on a Cache-Coherent Fabric. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (RECONFIG ’11). IEEE Computer Society, USA. 80–85. isbn:9780769545516 https://doi.org/10.1109/ReConFig.2011.4

Digital Library

[52]

Muhsen Owaida and Gustavo Alonso. 2020. Distributed Inference over Decision Tree Ensembles. https://github.com/fpgasystems/Distributed-DecisionTrees

[53]

Muhsen Owaida, Amit Kulkarni, and Gustavo Alonso. 2019. Distributed Inference over Decision Tree Ensembles on Clusters of FPGAs. ACM Trans. Reconfigurable Technol. Syst., 12, 4 (2019), Article 17, Sept., 27 pages. issn:1936-7406 https://doi.org/10.1145/3340263

Digital Library

[54]

Larry Peterson, Tom Anderson, David Culler, and Timothy Roscoe. 2003. A Blueprint for Introducing Disruptive Technology into the Internet. SIGCOMM Comput. Commun. Rev., 33, 1 (2003), Jan., 59–64. issn:0146-4833 https://doi.org/10.1145/774763.774772

Digital Library

[55]

Trusted Firmware Project. [n.d.]. Trusted Firmware-A (TF-A). https://developer.arm.com/tools-and-software/open-source-software/firmware/trusted-firmware/trusted-firmware-a Previously ARM Trusted Firmware.

[56]

Andrew Putnam, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, and Doug Burger. 2014. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services. SIGARCH Comput. Archit. News, 42, 3 (2014), June, 13–24. issn:0163-5964 https://doi.org/10.1145/2678373.2665678

Digital Library

[57]

Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, and Jason Cong. 2018. High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’18). Association for Computing Machinery, New York, NY, USA. 291. isbn:9781450356145 https://doi.org/10.1145/3174243.3174987

Digital Library

[58]

Shahin Roozkhosh and Renato Mancuso. 2020. The Potential of Programmable Logic in the Middle: Cache Bleaching. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 296–309. https://doi.org/10.1109/RTAS48715.2020.00006

[59]

Behzad Salami, Osman Unsal, and Adrian Cristal. 2018. Fault Characterization Through FPGA Undervolting. In 2018 28th International Conference on Field Programmable Logic and Applications (FPL). 85–853. https://doi.org/10.1109/FPL.2018.00023

[60]

Jasmin Schult, Daniel Schwyn, Michael Giardino, David Cock, Reto Achermann, and Timothy Roscoe. 2021. Declarative Power Sequencing. ACM Trans. Embed. Comput. Syst., 20, 5s (2021), Article 84, sep, 21 pages. issn:1539-9087 https://doi.org/10.1145/3477039

Digital Library

[61]

NXP Semiconductors. 2014. I2C-bus specification and user manual. https://www.nxp.com/docs/en/user-guide/UM10204.pdf Rev. 6.

[62]

David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees Vissers, and Raymond Carley. 2015. Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. In Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM ’15). IEEE Computer Society, USA. 36–43. isbn:9781479999699 https://doi.org/10.1109/FCCM.2015.12

Digital Library

[63]

David Sidler, Monica Chiosa, Zhenhao He, Mario Ruiz, Kimon Karras, and Lisa Liu. 2020. Scalable Network Stack supporting TCP/IP, RoCEv2, UDP/IP at 10-100Gbit/s. https://github.com/fpgasystems/fpga-network-stack.git

[64]

David Sidler, Zeke Wang, Monica Chiosa, Amit Kulkarni, and Gustavo Alonso. 2020. StRoM: Smart Remote Memory. In Proceedings of the Fifteenth European Conference on Computer Systems (EuroSys ’20). Association for Computing Machinery, New York, NY, USA. Article 29, 16 pages. isbn:9781450368827 https://doi.org/10.1145/3342195.3387519

Digital Library

[65]

Jeffrey Stuecheli, Bart Blaner, CR Johns, and MS Siegel. 2015. CAPI: A Coherent Accelerator Processor Interface. IBM Journal of Research and Development, 59, 1 (2015), 7:1–7:7. https://doi.org/10.1147/JRD.2014.2380198

Digital Library

[66]

J. Stuecheli, W. J. Starke, J. D. Irish, L. B. Arimilli, D. Dreps, B. Blaner, C. Wollbrink, and B. Allison. 2018. IBM POWER9 Opens up a New Era of Acceleration Enablement: OpenCAPI. IBM J. Res. Dev., 62, 4–5 (2018), July, 8:1–8:8. issn:0018-8646 https://doi.org/10.1147/JRD.2018.2856978

Digital Library

[67]

K. Sudan, K. Rajamani, W. Huang, and J. B. Carter. 2012. Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall. IEEE Trans. Comput., 61, 12 (2012), dec, 1697–1710. issn:1557-9956 https://doi.org/10.1109/TC.2012.119

Digital Library

[68]

System Management Interface Forum. 2018. System Management Bus (SMBus) Specification. http://www.smbus.org/specs/index.html v3.1.

[69]

System Management Interface Forum (SMIF), Inc. 2020. PMBussuperscript TM Power System Management Protocol Specification, revision 1.2. http://www.powersig.org/

[70]

Neil C. Thompson and Svenja Spanuth. 2021. The Decline of Computers as a General Purpose Technology. Commun. ACM, 64, 3 (2021), Feb., 64–72. issn:0001-0782 https://doi.org/10.1145/3430936

Digital Library

[71]

Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, and Phong Vo. 2018. Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. In 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). 6–9. https://doi.org/10.1109/DSN-W.2018.00013

[72]

Steven J. Vaughan-Nichols. 2017. MINIX: Intel’s hidden in-chip operating system. Online. https://www.zdnet.com/article/minix-intels-hidden-in-chip-operating-system/

[73]

Brian White, Jay Lepreau, Leigh Stoller, Robert Ricci, Shashi Guruprasad, Mac Newbold, Mike Hibler, Chad Barb, and Abhijeet Joglekar. 2002. An Integrated Experimental Environment for Distributed Systems and Networks. In Proceedings of the 5th Symposium on Operating Systems Design and Implementation (Copyright Restrictions Prevent ACM from Being Able to Make the PDFs for This Conference Available for Downloading) (OSDI ’02). USENIX Association, USA. 255–270. isbn:9781450301114

[74]

Wikipedia. 2022. ATX. https://en.wikipedia.org/wiki/ATX

[75]

Xilinx. 2018. VCU118 Evaluation Board User Guide. https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf

[76]

2020. Alveo U200 and U250 Data Center Accelerator Cards Data Sheet (v.1.3.1 ed.). https://www.xilinx.com/products/boards-and-kits/alveo/u250.html

[77]

2020. Alveo U280 Data Center Accelerator Card Data Sheet (v.1.3 ed.). https://www.xilinx.com/products/boards-and-kits/alveo/u280.html

[78]

Xilinx. 2021. UltraScale Architecture and Product Data Sheet: Overview. https://www.xilinx.com/support/documentation/data_sheets/ds890-ultrascale-overview.pdf DS890 (v4.0).

[79]

Yu Zhu, Zhenhao He, Wenqi Jiang, Kai Zeng, Jingren Zhou, and Gustavo Alonso. 2021. Distributed Recommendation Inference on FPGA Clusters. In 31st International Conference on Field-Programmable Logic and Applications, FPL 2021.

[80]

Patrick Ziegler. 2020. A Unified Approach to Simulation of Hybrid CPU/FPGA systems. Department of Computer Science, ETH Zurich.

Cited By

Asmussen NMiemietz THaas SRoitzsch M(2025)Distrusting cores by separating computation from isolationJournal of Systems Architecture10.1016/j.sysarc.2024.103328159(103328)Online publication date: Feb-2025
https://doi.org/10.1016/j.sysarc.2024.103328
Weingarten MHossle NRoscoe T(2024)High Throughput Hardware Accelerated CoreSight Trace Decoding2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546666(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546666
Suresh VMishra BJing YZhu ZJin NBlock CMantovani PGiri DZuckerman JCarloni LAdve S(2024)Mozart: Taming Taxes and Composing Accelerators with Shared-MemoryProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676896(183-200)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676896
Show More Cited By

Index Terms

Enzian: an open, general, CPU/FPGA platform for systems software research

Recommendations

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

The advent of FPGA acceleration platforms with direct coherent access to processor memory creates an opportunity for accelerating applications with irregular parallelism governed by large in-memory pointer-based data structures. This paper uses the ...
Nuclear Reactor Simulations on OpenCL FPGA Platform
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are becoming a promising choice as a heterogeneous computing component for scientific computing when floating-point optimized architectures are added to the current FPGAs. The maturing high-level synthesis (HLS) ...
Conjoining soft-core FPGA processors
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

February 2022

1164 pages

ISBN:9781450392051

DOI:10.1145/3503222

General Chairs:
Babak Falsafi
EPFL, Switzerland
,
Michael Ferdman
Stony Brook University, USA
,
Program Chairs:
Shan Lu
University of Chicago, USA
,
Tom Wenisch
University of Michigan, USA / Google, USA

Copyright © 2022 ACM.

Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

Sponsors

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2022

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Badges

Author Tags

Qualifiers

Research-article

Conference

ASPLOS '22

Sponsor:

ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

February 28 - March 4, 2022

Lausanne, Switzerland

Acceptance Rates

Overall Acceptance Rate 535 of 2,713 submissions, 20%

Upcoming Conference

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

25
Total Citations
View Citations
2,113
Total Downloads

Downloads (Last 12 months)280
Downloads (Last 6 weeks)23

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Asmussen NMiemietz THaas SRoitzsch M(2025)Distrusting cores by separating computation from isolationJournal of Systems Architecture10.1016/j.sysarc.2024.103328159(103328)Online publication date: Feb-2025
https://doi.org/10.1016/j.sysarc.2024.103328
Weingarten MHossle NRoscoe T(2024)High Throughput Hardware Accelerated CoreSight Trace Decoding2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546666(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546666
Suresh VMishra BJing YZhu ZJin NBlock CMantovani PGiri DZuckerman JCarloni LAdve S(2024)Mozart: Taming Taxes and Composing Accelerators with Shared-MemoryProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676896(183-200)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676896
Starc RKuchler TGiardino MKlimovic A(2024)Serverless? RISC more!Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies10.1145/3642977.3652095(15-24)Online publication date: 22-Apr-2024
https://dl.acm.org/doi/10.1145/3642977.3652095
Anand SFriedman MGiardino MAlonso GTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Skip It: Take Control of Your Cache!Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640407(1077-1094)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640407
Papon TMun JKaratsenidis KRoozkhosh SHoornaert DSanaullah ADrepper UMancuso RAthanassoulis M(2024)Effortless Locality on Data Systems Using Relational FabricIEEE Transactions on Knowledge and Data Engineering10.1109/TKDE.2024.338682736:12(7410-7422)Online publication date: Dec-2024
https://doi.org/10.1109/TKDE.2024.3386827
Gouveia ISheikh AShoker AFahmy SEsteves-Verissimo P(2024)Resilient and Secure Programmable System-on-Chip Accelerator Offload2024 43rd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS64841.2024.00016(52-65)Online publication date: 30-Sep-2024
https://doi.org/10.1109/SRDS64841.2024.00016
Ji HVanavasam SZhou YXia QHuang JYuan YWang RGupta PChitlur BJeong IKim N(2024)Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00110(1504-1517)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00110
Grindley EGray TWilkinson JVaux CArdron ADeeley JElliott AThandassery Sumithran NFahmy S(2024)The NAIL Accelerator Interface Layer for Low Latency FPGA OffloadIEEE Access10.1109/ACCESS.2024.348346012(155976-155989)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3483460
Fiedler BLiu ZCock DRoscoe T(2024)Verified Fault Handling for Modern Board Management ControllersFormal Aspects of Component Software10.1007/978-3-031-71261-6_2(21-38)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1007/978-3-031-71261-6_2
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents