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Very Low Power High-Frequency Floating Point FPGA PID Controller

Published: 09 June 2022 Publication History

Abstract

In this work, we present the design and implementation of a floating-point Proportional-Integral-Derivative (PID) controller accelerator which achieves a high rate of 637 K samples per second at 20 mW of power consumption, implemented on a Lattice UP5K FPGA. Our system delivers over 70 × the performance compared to a microprocessor with comparable size and power constraints, and 5 × the power efficiency compared to a larger and more capable ARM Cortex-M4F with hardware floating-point operators. We achieve such high performance using a systolic array design using simplified hardware floating-point operators implemented using embedded DSP blocks on a low-power FPGA. We support simple handling of complex reference such as sinusoidal signals by storing the reference as a time series in on-chip block RAM. The level of high performance, low power, and small size we achieve is necessary for our target application of micro, or insect-scale robotics.

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Cited By

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  • (2024)A Hardware Implementation of the PID Algorithm Using Floating-Point ArithmeticElectronics10.3390/electronics1308159813:8(1598)Online publication date: 22-Apr-2024
  • (2023)On the Functional Properties of Automatically Generated Fixed-Point Controllers2023 9th International Conference on Control, Decision and Information Technologies (CoDIT)10.1109/CoDIT58514.2023.10284265(786-791)Online publication date: 3-Jul-2023

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Published In

cover image ACM Other conferences
HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies
June 2022
114 pages
ISBN:9781450396608
DOI:10.1145/3535044
This work is licensed under a Creative Commons Attribution International 4.0 License.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 June 2022

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Author Tags

  1. FPGA acceleration
  2. PID controller
  3. floating point

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  • Short-paper
  • Research
  • Refereed limited

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HEART2022

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HEART '22 Paper Acceptance Rate 10 of 21 submissions, 48%;
Overall Acceptance Rate 22 of 50 submissions, 44%

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Cited By

View all
  • (2024)A Hardware Implementation of the PID Algorithm Using Floating-Point ArithmeticElectronics10.3390/electronics1308159813:8(1598)Online publication date: 22-Apr-2024
  • (2023)On the Functional Properties of Automatically Generated Fixed-Point Controllers2023 9th International Conference on Control, Decision and Information Technologies (CoDIT)10.1109/CoDIT58514.2023.10284265(786-791)Online publication date: 3-Jul-2023

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