Resource sharing beyond FQ: 35K users at 100Gbps

Core-stateless resource sharing solutions implemented in P4 hardware data planes have been proposed in the past few years. They share the idea of tagging packets with special values at the network edge that are then solely used for deciding how to handle packets in the network in case of congestion. Though the scheduler of our Core-Stateless Active Queue management (CSAQM) was implemented in P4 and was evaluated on Intel Tofino ASIC, the packet marker have only had a DPDK-based software implementation so far. In this demo, we present the full data plane implementation of CSAQM. Both packet marking and packet scheduling are executed by an Intel Tofino ASIC. We demonstrate the scalability of our implementation by showing policy enforcement among up to 35000 subscribers at a 100 Gbps bottleneck using only a single queue. In addition, we also present the resource sharing and isolation properties of CSAQM between flows with different rate control strategies, resulting in flow-specific congestion signals (drop probabilities) by design.