invited-talk

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper

Authors:

Eric BeyneAuthors Info & Claims

SLIP '22: Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding

Article No.: 3, Pages 1 - 5

https://doi.org/10.1145/3557988.3569716

Published: 27 January 2023 Publication History

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Abstract

Technology node scaling is driven by the need to increase system performance, but it also leads to a significant power integrity bottleneck, due to the associated back-end-of-line (BEOL) scaling. Power integrity degradation induced by on-chip Power Delivery Network (PDN) IR drop is a result of increased power density and number of metal layers in the BEOL and their resistivity. Meanwhile, signal routing limits the SoC performance improvements due to increased routing congestion and delays. To conquer these issues, we introduce a disruptive technology: wafer backside (BS) connection to realize chip BS PDN (BSPDN) and BS signal routing. We first provide some key wafer processes features that were developed at imec to enable this technology. Further, we show benefits of this technology by demonstrating a large improvement in chip power integrity and performance after applying this technology to BSPDN and BS routing with a sub-2nm technology node design rule. Challenges and outlook of the BS technology are also discussed before conclusion of this paper.

References

[1]

R. Chen et al., "Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation---Part I: CNFET Transistor Optimization," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 4, pp. 432--439, Apr. 2022

Crossref

Google Scholar

[2]

H. Mertens, et al., "Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space" 2021 Symposium on VLSI Technology, Jun. 2021.

Google Scholar

[3]

P. Schuddinck et al., "PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022

Crossref

Google Scholar

[4]

A. Farokhnejad et al., "Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis," 2022 IEEE International Interconnect Technology Conference (IITC), Jun. 2022

Crossref

Google Scholar

[5]

R. Chen et al., "Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances-Part I: Pristine MWCNT," IEEE Transactions on Electron Devices, pp. 1--8, 2018

Crossref

Google Scholar

[6]

A. Veloso et al., "Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022

Crossref

Google Scholar

[7]

R. Chen et al., "Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022

Crossref

Google Scholar

[8]

G. Sisto et al., "IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs," 2021 IEEE International Interconnect Technology Conference (IITC), Jul. 2021

Crossref

Google Scholar

[9]

R. Chen et al., "3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes," 2020 IEEE International Electron Devices Meeting (IEDM), Dec. 2020

Crossref

Google Scholar

[10]

R. Chen et al., "Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network," 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022.

Google Scholar

[11]

R. Chen et al., "Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node," 2021 IEEE International Electron Devices Meeting (IEDM), Dec. 2021

Crossref

Google Scholar

[12]

J. Ryckaert et al., "Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery," 2019 Electron Devices Technology and Manufacturing Conference (EDTM), Mar. 2019

Crossref

Google Scholar

[13]

A. Veloso et al., "Insights into Scaled Logic Devices Connected from Both Wafer Sides" 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022.

Google Scholar

Cited By

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Woo SLee HShin YHan MGo YKim JLee HKim HSong T(2024)Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546599(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546599
Yang WJian TLin YLin R(2024)Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS62602.2024.10808511(692-696)Online publication date: 7-Nov-2024
https://doi.org/10.1109/APCCAS62602.2024.10808511

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Published In

SLIP '22: Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding

November 2022

46 pages

ISBN:9781450395366

DOI:10.1145/3557988

General Chair:
Mustafa Badaroglu
Qualcomm, Belgium
,
Program Chair:
Shantanu Dutt
University of Illinois at Chicago, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

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Published: 27 January 2023

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ICCAD '22

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SIGDA

ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

November 3, 2022

California, San Diego

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Woo SLee HShin YHan MGo YKim JLee HKim HSong T(2024)Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546599(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546599
Yang WJian TLin YLin R(2024)Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS62602.2024.10808511(692-696)Online publication date: 7-Nov-2024
https://doi.org/10.1109/APCCAS62602.2024.10808511

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Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs

SRAM write-ability improvement with transient negative bit-line voltage

Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs

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