research-article

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

Authors:

Giovanni Ansaloni,

Marina Zapater,

Eduard Alarcón,

David AtienzaAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 561 - 566

https://doi.org/10.1145/3566097.3567952

Published: 31 January 2023 Publication History

Abstract

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to cope with limited inter-chiplet routing resources, which complicate the design of the data interconnect and the power delivery network. Emerging in-package wireless technology is a promising strategy to address these challenges, as it allows to implement flexible chiplet interconnects while freeing package resources for power supply connections. To assess the capabilities of such an approach and its impact from a full-system perspective, herein we present an exploration of the performance of in-package wireless communication, based on dedicated extensions to the gem5-X simulator. We consider different Medium Access Control (MAC) protocols, as well as applications with different runtime profiles, showcasing that current in-package wireless solutions are competitive with wired chiplet interconnects. Our results show how in-package wireless solutions can outperform wired alternatives when running artificial intelligence workloads, achieving up to a 2.64× speed-up when running deep neural networks (DNNs) on a chiplet-based system with 16 cores distributed in four clusters.

References

[1]

Sergi Abadal et al. 2022. Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. IEEE Wireless Communications (2022).

[2]

ARM. 2022. Arm Cortex-A75 Processor. https://developer.arm.com/Processors/Cortex-A75

[3]

Nathan Binkert et al. 2011. The Gem5 Simulator. SIGARCH Comput. Archit. News (2011).

[4]

Ken Chatfield et al. 2014. Return of the Devil in the Details: Delving Deep into Convolutional Nets. (2014). http://arxiv.org/abs/1405.3531

[5]

Wonje Choi et al. 2018. On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems. IEEE TC (2018).

[6]

Yi Lin Chuang et al. 2013. Unified Methodology for Heterogeneous Integration with CoWoS Technology. In IEEE ECTC.

[7]

Karthi Duraisamy et al. 2017. Multicast-Aware High-Performance Wireless Network-on-Chip Architectures. IEEE TVLSIS (2017).

[8]

Vimuth Fernando et al. 2019. Replica: A Wireless Manycore for Communication-Intensive and Approximate Data. In ACM ASPLOS.

Digital Library

[9]

Antonio Franques et al. 2021. Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores. In DATE.

[10]

Sri Harsha Gade and Sujay Deb. 2017. HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures. IEEE TC (2017).

[11]

Robert Guirado et al. 2021. Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package. In ASP-DAC.

[12]

Andrew G. Howard et al. 2017. MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications. (2017). http://arxiv.org/abs/1704.04861

[13]

Gabriel H. Loh et al. 2021. Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. In IEEE DATE.

[14]

Ravi Mahajan et al. 2016. Embedded Multi-die Interconnect Bridge (EMIB): A High Density, High Bandwidth Packaging Interconnect. In IEEE ECTC.

[15]

John D. McCalpin. 1995. Memory Bandwidth and Machine Balance in Current High Performance Computers. IEEE TCCA Newsletter (1995).

[16]

Robert M Metcalfe and David R Boggs. 1976. Ethernet: Distributed Packet Switching for Local Computer Networks. Commun. ACM (1976).

[17]

Samuel Naffziger et al. 2021. Pioneering chiplet technology and design for the AMD EPYC and Ryzen processor families: Industrial product. In ISCA.

[18]

Saptadeep Pal et al. 2018. A Case for Packageless Processors. In IEEE HPCA.

[19]

Yasir M. Qureshi et al. 2021. Gem5-X: A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization. ACM TACO (2021).

[20]

Mark Sandler et al. 2018. MobileNetV2: Inverted Residuals and Linear Bottlenecks. (2018). http://arxiv.org/abs/1801.04381

[21]

Debendra D. Sharma. 2022. Universal Chiplet Interconnect Express (UCIe): Building an open chiplet ecosystem. Technical Report.

[22]

Synopsis. 2022. DesignWare Die-to-Die IP Solutions. https://www.synopsys.com/designware-ip/interface-ip/die-to-die.html

[23]

Korkut K. Tokgoz et al. 2018. A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver. In IEEE ISSCC.

[24]

S.C. Woo et al. 1995. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA.

[25]

Sam Likun Xi et al. 2015. Quantifying Sources of Error in McPAT and Potential Impacts on Architectural Studies. IEEE HPCA.

Cited By

Medina RHuang DAnsaloni GZapater MAtienza D(2023)REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321912(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321912

Index Terms

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits
    1. 3D integrated circuits
    2. Interconnect
      1. Radio frequency and wireless interconnect

Recommendations

Design of multi-channel wireless NoC to improve on-chip communication capacity
NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Many-core chip design has become a popular means to sustain the exponential growth of chip-level computing performance. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication ...
System-level interconnect architecture exploration for custom memory organizations
ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

For data dominated applications, power consumption and memory bandwidth bottlenecks can be significantly alleviated with a custom memory organization. However, this potentially entails complex memory interconnections and a large routing overhead. This ...
Package level interconnect options
SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction

Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IPSJ
IEEE CAS
IEEE CEDA
IEICE

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 January 2023

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ASPDAC '23

Sponsor:

SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

Acceptance Rates

ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
302
Total Downloads

Downloads (Last 12 months)163
Downloads (Last 6 weeks)31

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Medina RHuang DAnsaloni GZapater MAtienza D(2023)REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321912(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321912

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents