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Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning

Published: 05 June 2023 Publication History

Abstract

Low-precision formats have been proposed and applied to deep learning algorithms to speed up training and inference. This paper proposes a novel multiple-precision multiplication unit(MU) for deep learning. The proposed MU supports four types of precision for floating-point(FP) numbers-FP8-E4M3, FP8-E5M2, FP16, FP32-and 8-bit fixed-point(FIX) numbers. The MU can execute four parallel FP8 and eight parallel FIX8 multiplications simultaneously in one cycle, or four parallel FP16 multiplications fully pipelined with a latency of one, or one FP32 multiplication with a latency of one cycle. The simultaneous execution of FIX8 and FP8 can meet the requirements of the specific deep learning algorithms. Thanks to the low-precision-combination(LPC) and vectorization design method, multiplication in any precision can get 100% utilization of the multiplier resources, and the MU can adopt a lower clock delay to achieve better performance in all data types. Compared with the existing multiple-precision units designed for deep learning, this MU can support more types of low-precision formats by lower area overhead; and exhibits higher throughput at FIX8 with at least 8× improvement.

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  1. Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning

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      cover image ACM Conferences
      GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023
      June 2023
      731 pages
      ISBN:9798400701252
      DOI:10.1145/3583781
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      Published: 05 June 2023

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      Author Tags

      1. deep learning
      2. low-precision
      3. lpc
      4. multiple-precision
      5. multiplication unit

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      • NSFC
      • HNNSFC

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      GLSVLSI '23
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      GLSVLSI '23: Great Lakes Symposium on VLSI 2023
      June 5 - 7, 2023
      TN, Knoxville, USA

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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