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Performance improvement with circuit-level speculation

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Tong Liu,

Shih-Lien LuAuthors Info & Claims

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Pages 348 - 355

https://doi.org/10.1145/360128.360166

Published: 01 December 2000 Publication History

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Cited By

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A KGowda C(2021)An Efficient 32-bit Ladner Fischer Adder derived using Han-Carlson2021 IEEE International Conference on Mobile Networks and Wireless Communications (ICMNWC)10.1109/ICMNWC52512.2021.9688464(1-4)Online publication date: 3-Dec-2021
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Bonnot JCamus VDesnos KMenard D(2018)Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits2018 26th European Signal Processing Conference (EUSIPCO)10.23919/EUSIPCO.2018.8553451(677-681)Online publication date: Sep-2018
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Camus VCacciotti MSchlachter JEnz C(2018)Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back AdderIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2018.28517498:4(746-757)Online publication date: Dec-2018
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MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

December 2000

357 pages

ISBN:1581131968

DOI:10.1145/360128

Chairmen:
Andrew Wolfe
S3 Incorporated
,
Michael Schlansker
Hewlett-Packard

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 December 2000

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MICRO 33 Paper Acceptance Rate 31 of 110 submissions, 28%;

Overall Acceptance Rate 455 of 2,084 submissions, 22%

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A KGowda C(2021)An Efficient 32-bit Ladner Fischer Adder derived using Han-Carlson2021 IEEE International Conference on Mobile Networks and Wireless Communications (ICMNWC)10.1109/ICMNWC52512.2021.9688464(1-4)Online publication date: 3-Dec-2021
https://doi.org/10.1109/ICMNWC52512.2021.9688464
Bonnot JCamus VDesnos KMenard D(2018)Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits2018 26th European Signal Processing Conference (EUSIPCO)10.23919/EUSIPCO.2018.8553451(677-681)Online publication date: Sep-2018
https://doi.org/10.23919/EUSIPCO.2018.8553451
Camus VCacciotti MSchlachter JEnz C(2018)Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back AdderIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2018.28517498:4(746-757)Online publication date: Dec-2018
https://doi.org/10.1109/JETCAS.2018.2851749
Shrestha R(2017)High-speed and low-power VLSI-architecture for inexact speculative adder2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT.2017.7939644(1-4)Online publication date: Apr-2017
https://doi.org/10.1109/VLSI-DAT.2017.7939644
Franceschi MCamus VIbrahim AEnz CValle M(2017)Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders2017 New Generation of CAS (NGCAS)10.1109/NGCAS.2017.40(41-44)Online publication date: Sep-2017
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SHIOYA RANDO H(2016)Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy EfficiencyIEICE Transactions on Information and Systems10.1587/transinf.2015EDP7270E99.D:3(630-640)Online publication date: 2016
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Camus VSchlachter JEnz C(2016)A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precisionProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897964(1-6)Online publication date: 5-Jun-2016
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Esposito DDe Caro DStrollo A(2016)Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed OperandsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2016.256469963:8(1200-1209)Online publication date: Aug-2016
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Rahimi ABenini LGupta R(2016)Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to SoftwareProceedings of the IEEE10.1109/JPROC.2016.2518864104:7(1410-1448)Online publication date: Jul-2016
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Camus VSchlachter JEnz C(2015)Energy-efficient digital design through inexact and approximate arithmetic circuits2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2015.7182028(1-4)Online publication date: Jun-2015
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Enhancing instruction level parallelism through compiler-controlled speculation

Boosting SMT Performance by Speculation Control

Exploiting Locality to Improve Circuit-Level Timing Speculation

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Enhancing instruction level parallelism through compiler-controlled speculation

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Exploiting Locality to Improve Circuit-Level Timing Speculation

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