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Interference in multiprocessor computer systems with interleaved memory

Published: 01 June 1976 Publication History
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  • Abstract

    This paper analyzes the memory interference caused by several processors simultaneously using several memory modules. Exact results are computed for a simple model of such a system. The limiting value is derived for the relative degree of memory interference as the system size increases. The model of the limiting behavior of the system yields approximate results for the simple model and also suggests that the results are valid for a much larger class of models, including those more nearly like real systems than the simple model. The assumptions and results of the simple model are tested against some measurements of program behavior and simulations of systems using memory references from real programs. The model results provide a good indication of the performance that should be expected from real systems of this type.

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    Published In

    cover image Communications of the ACM
    Communications of the ACM  Volume 19, Issue 6
    June 1976
    49 pages
    ISSN:0001-0782
    EISSN:1557-7317
    DOI:10.1145/360238
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 June 1976
    Published in CACM Volume 19, Issue 6

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    Author Tags

    1. interleaved memory
    2. memory
    3. memory interference
    4. multiprocessing
    5. trace driven simulation

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